adau1461 Analog Devices, Inc., adau1461 Datasheet - Page 58

• Manufacturer Part Number: adau1461
• Description: Sigmadsp Stereo, Low Power, 96 Khz, 24-bit Audio Codec With Integrated Pll Adau1461
• Manufacturer: Analog Devices, Inc.

ADAU1461
R12: ALC Control 1, 16,402 (0x4012)
Bit 7
Table 44. ALC Control 1 Register
Bits
[7:4]
[3:0]
Bit Name
ALCHOLD[3:0]
ALCTARG[3:0]
Bit 6
ALCHOLD[3:0]
Description
ALC hold time. The ALC hold time is the amount of time that the ALC waits after a decrease in input level before
increasing the gain to achieve the target level. The recommended minimum setting is 21 ms (0011) to prevent
distortion of low frequency signals. The hold time doubles with every 1-bit increase.
Setting
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
ALC target. The ALC target sets the desired ADC input level. The PGA gain is adjusted by the ALC to reach this
target level. The recommended target level is between −16 dB and −10 dB to accommodate transients without
clipping the ADC.
Setting
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Bit 5
Bit 4
Hold Time
2.67 ms (default)
5.34 ms
10.68 ms
21.36 ms
42.72 ms
85.44 ms
170.88 ms
341.76 ms
683.52 ms
1.367 sec
2.7341 sec
5.4682 sec
10.936 sec
21.873 sec
43.745 sec
87.491 sec
ALC Target
−28.5 dB (default)
−27 dB
−25.5 dB
−24 dB
−22.5 dB
−21 dB
−19.5 dB
−18 dB
−16.5 dB
−15 dB
−13.5 dB
−12 dB
−10.5 dB
−9 dB
−7.5 dB
−6 dB
Rev. 0 | Page 58 of 88
Bit 3
Bit 2
ALCTARG[3:0]
Bit 1
Bit 0