adau1461 Analog Devices, Inc., adau1461 Datasheet - Page 38

• Manufacturer Part Number: adau1461
• Description: Sigmadsp Stereo, Low Power, 96 Khz, 24-bit Audio Codec With Integrated Pll Adau1461
• Manufacturer: Analog Devices, Inc.

ADAU1461
I
Figure 51 shows the format of a single-word write operation.
Every ninth clock pulse, the ADAU1461 issues an acknowledge
by pulling SDA low.
Figure 52 shows the format of a burst mode write sequence. This
figure shows an example of a write to sequential single-byte
registers. The ADAU1461 increments its subaddress register
after every byte because the requested subaddress corresponds
to a register or memory area with a 1-byte word length.
Figure 53 shows the format of a single-word read operation. Note
that the first R/ W bit is 0, indicating a write operation. This is
because the subaddress still needs to be written to set up the
internal address. After the ADAU1461 acknowledges the receipt
of the subaddress, the master must issue a repeated start command
followed by the chip address byte with the R/ W bit set to 1 (read).
S
S
S
S
2
C Read and Write Operations
Chip address,
R/W = 0
Chip address,
R/W = 0
Chip address,
R/W = 0
Chip address,
R/W = 0
AS
AS
AS
Subaddress
high byte
Subaddress
high byte
Subaddress high
byte
AS
Subaddress high byte
AS
AS
Subaddress
low byte
Subaddress
low byte
AS
Figure 51. Single-Word I
Figure 53. Single-Word I
Figure 52. Burst Mode I
Figure 54. Burst Mode I
Subaddress low
byte
Rev. 0 | Page 38 of 88
AS
AS
Data
Byte 1
AS
S
2
2
2
2
C Write Format
C Read Format
C Write Format
C Read Format
Chip address,
R/W = 1
This causes the ADAU1461 SDA to reverse and begin driving
data back to the master. The master then responds every ninth
pulse with an acknowledge pulse to the ADAU1461.
Figure 54 shows the format of a burst mode read sequence. This
figure shows an example of a read from sequential single-byte
registers. The ADAU1461 increments its subaddress register
after every byte because the requested subaddress corresponds
to a register or memory area with a 1-byte word length. The
ADAU1461 always decodes the subaddress and sets the auto-
increment circuit so that the address increments after the
appropriate number of bytes.
Figure 51 to Figure 54 use the following abbreviations:
S = start bit
P = stop bit
AM = acknowledge by master
AS = acknowledge by slave
Subaddress low byte
AS
AS
Data
Byte 2
S
AS
AS
Data
Byte 1
Chip address,
R/W = 1
Data
Byte 3
AS
AM
AS
Data Byte 1
Data
Byte 2
AS
Data
Byte 4
Data
Byte 1
AM
AS
…
…
P
P
P
P