adau1373 Analog Devices, Inc., adau1373 Datasheet - Page 47

• Manufacturer Part Number: adau1373
• Description: Low Power Codec With Speaker And Headphone Amplifier Adau1373
• Manufacturer: Analog Devices, Inc.

DPLL
The DPLL consists of a phase comparator, followed by a high-
pass filter and integrators. The following equation shows the
relationship of input-to-output frequency:
where:
f
f
N
or 1024, using Bits[3:0] (DPLLA_NDIV) in Register 0x28 for
DPLLA and Bits[3:0] (DPLLB_NDIV) Register 0x2F for DPLLB.
M
DPLL Divider Example
f
f
N
Setting N
be set to 1.
Core Clock
The core clock is derived directly from the external clock at the
MCLK1 or MCLK2 pins or from the PLL. The PLLA_EN bit for
PLLA (Bit 0 in Address 0x2E) and the PLLB_EN bit for PLLB
(Bit 0 in Address 0x35) can be used to enable or disable the
PLL. Clocks for the converters, the serial ports, and the DSP are
derived from the core clock. The core clock rate is always an
integer multiple of the desired sample rate used inside the part.
Case 1—PLL Bypassed (Using External Clock as Core Clock)
If the PLL is bypassed, the clock available at MCLK1 (Ball C2)
or MCLK2 (Ball D1) is used as the core clock. Therefore, f
As the PLL is bypassed, the frequency of the clock at the MCLKx
pins must be set properly, using the clock divider bits, CLK1SDIV,
Bits[5:3], and MCLK1DIV, Bits[2:0], in Register 0x40 for PLLA and
CLK2SDIV, Bits[5:3], and MCLK2DIV, Bits[2:0] in Register 0x42
for PLLB. The required external clock rate can be determined by
the following equation, in which J and K are the clock dividers:
See Table 14, Table 15, and Table 16 for some possible options
for external clock rates. Note that clock rates greater than 50 MHz
require careful attention to the clock driver and board layout to
maintain signal integrity.
Be sure that this clock is available to the MCLKx input pins
before enabling the COREN bit (Bit 7, core clock enable) in
Register 0x40.
Case 2—PLL Enabled
The internal PLL can be used to generate the core clock from
the external clock. The internal PLL has two modes of operation:
integer mode and fractional mode. Therefore, f
OUT
IN
IN
OUT
D
D
D
is the DPLL input frequency (8 kHz to 8 MHz).
= 8 kHz
is the divider. It can be set to 1, 2, 4, 8, 16, 32, 64, 128, 256, 512,
= 8 × 1024/8 = 1.024
is the multiplier (fixed internally to 1024).
is the DPLL output frequency (8 MHz to 27 MHz).
= 8 MHz
f
f
OUT
IN
= 256 × f
= (f
D
to 1 results in f
IN
/N
S
D
) × M
× (J + 1) × (K + 1)
D
OUT
≥ 8 MHz. Therefore, N
CORE
= f
D
should
PLL
CORE
.
= f
Rev. 0 | Page 47 of 296
IN
.
APLL
The APLL provides the fine resolution required to generate clocks
for the internal blocks. It uses either the clock input at the MCLK1
pin (Ball C2) or a DPLL output as a reference to generate the core
clock. The PLL can be set for either integer or fractional mode.
The PLL multiplier and divider (X, R, M, and N) are programmed
using Register 0x29 to Register 0x2D for PLLA and Register 0x30
to Register 0x34 for PLLB. The PLL can accept input frequencies in
the range of 8 MHz to 27 MHz, either directly from an external
source, if the external clock input is greater than 8 MHz, or from
the DPLL, if the external clock input is within a range of 8 kHz
to 8 MHz. The PLL lock range is 45.158 MHz to 49.152 MHz.
This sets the PLL output frequency based on the sample rate
governed by the following equation:
where J, K = 0, 1, 2, …7.
The APLL can be used in either integer mode or fractional mode.
Integer Mode
Integer mode is used when the MCLK frequency is an integer
multiple of the PLL output (1024 × f
the following equation:
where f
For example, if f
Therefore, R and X are set as follows: R = 4, and X = 1 (default).
In integer mode, the values set for N and M are ignored. Table 13
shows common integer PLL parameter settings for f
sampling rates.
Fractional Mode
Fractional mode is used when the available MCLK is a fractional
multiple of the desired PLL output; it is governed by the following:
For example, MCLK = 12 MHz and f
The PLL output is 1024 × f
To find the values of R, N, and M, use the following equation:
where f
See Table 11 and Table 12 for common fractional PLL parameter
settings for 44.1 kHz and 48 kHz sampling rates.
f
f
f
R/X = 49.152 MHz/12.288 MHz = 4
f
PLL Output = 1024 × 48 kHz = 49.152 MHz
f
(R + (N/M))/X = 49.152 MHz/12 MHz = 4 + (12/125)
PLL
PLL
PLL
PLL
PLL
PLL
PLL
f
= 256 × f
IN
= (R/X) × f
(PLL Required Output) = 1024 × 48 kHz = 49.152 MHz
= f
= f
= 1024 × f
= 49.152, and f
IN
IN
× (R + (N/M))/X
× (R + (N/M))/X
IN
÷X
S
= 12.288 MHz and f
× (J + 1) × (K + 1)
Figure 94. APLL Block Diagram
IN
S
× (R + N/M)
IN
S
= 12 MHz.
.
CLOCK DIVIDER
S
) frequency, governed by
S
= 48 kHz.
S
TO PLL
= 48 kHz, then
ADAU1373
S
= 48 kHz