palce22v10h-10si Lattice Semiconductor Corp., palce22v10h-10si Datasheet - Page 3

• Manufacturer Part Number: palce22v10h-10si
• Description: 24-pin Ee Cmos Zero Power Versatile Pal Device
• Manufacturer: Lattice Semiconductor Corp.

Variable Input/Output Pin Ratio
The PALCE22V10 has twelve dedicated input lines, and each macrocell output can be an I/O pin.
Buffers for device inputs have complementary outputs to provide user-programmable input signal
polarity. Unused input pins should be tied to V
Registered Output Configuration
Each macrocell of the PALCE22V10 includes a D-type flip-flop for data storage and
synchronization. The flip-flop is loaded on the LOW-to-HIGH transition of the clock input. In the
registered configuration (S
Combinatorial I/O Configuration
Any macrocell can be configured as combinatorial by selecting the multiplexer path that bypasses
the flip-flop (S
CLK
1
= 1). In the combinatorial configuration, the feedback is from the pin.
D Q
AR
SP
0
1
Q
1
= 0), the array feedback is from Q of the flip-flop.
Figure 1. Output Logic Macrocell Diagram
PALCE22V10 and PALCE22V10Z Families
S 1
1 0
1 1
0 0
0 1
S 0
CC
or GND.
0 = Programmed EE bit
1 = Erased (charged) EE bit
I/O n
S
0
0
1
1
1
S
0
1
0
1
0
Registered/Active Low
Registered/Active High
Combinatorial/Active Low
Combinatorial/Active High
Output Configuration
16564E-004
3