km68v1000blg-7l Samsung Semiconductor, Inc., km68v1000blg-7l Datasheet - Page 8

• Manufacturer Part Number: km68v1000blg-7l
• Description: 128k X 8bit Low Power And Low Voltage Cmos Statinc Ram
• Manufacturer: Samsung Semiconductor, Inc.

DATA RETENTION WAVE FORM
KM68V1000B, KM68U1000B Family
CS
CS
TIMING WAVEFORM OF WRITE CYCLE(3)
1
V
3.0/2.7V
2.2V
V
CS
GND
2
V
3.0/2.7V
CS
V
0.4V
GND
Address
CS
CS
WE
Data in
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS
2. t
3. t
4. t
CC
DR
CC
DR
controlled
controlled
CS
t
applied in case a write ends as CS
WP
CW
AS
WR
1
2
1
2
2
is measured from the address valid to the beginning of write.
is measured from the begining of write to the end of write.
is measured from the CS
is measured from the end of write to the address change. t
going high and WE going low : A write end at the earliest transition among CS
1)
1)
1. 3.0V for KM68V1000B Family , 2.7V for KM68U1000B Family
1
going low or CS
2
going to low.
High-Z
t
SDR
t
t
SDR
AS(3)
1
, a high CS
2
going high to the end of write.
(CS
1
Controlled)
2
and a low WE. A write begins at the latest transition among CS
Data Retention Mode
Data Retention Mode
WR(1)
t
AW
CS
t
t
WC
CS
t
CW(2)
CW(2)
applied in case a write ends as CS
1
2
V
t
WP(1)
CC
0.2V
- 0.2V
t
1
DW
going high, CS
Data Valid
t
WR(4)
t
DH
2
going low and WE going high,
t
RDR
High-Z
1
t
RDR
or WE going high t
CMOS SRAM
1
goes low,
Revision 2.0
March 1998
WR(2)