ns32491 National Semiconductor Corporation, ns32491 Datasheet - Page 3

• Manufacturer Part Number: ns32491
• Description: Serial Network Interface
• Manufacturer: National Semiconductor Corporation

Figures 4 5 and 6 illustrate the transmit timing
3 0 Functional Description
mains high transmit data (TXD) is encoded out to the trans-
mit-driver pair (TX
inputs must meet the setup and hold time requirements with
respect to the rising edge of transmit clock Transmission
ends with the transmit enable input going low The last tran-
sition is always positive at the transmit output pair It will
occur at the center of the bit cell if the last bit is one or at
the boundary of the bit cell if the last bit is zero
The differential line driver provides ECL like signals to the
transceiver with typically 5 ns rise and fall times It can drive
up to 50 meters of twisted pair AUI Ethernet transceiver
cable These outputs are source followers which need ex-
ternal 270X pulldown resistors to ground Two different
modes full-step or half-step can be selected with SEL in-
put With SEL low transmit
transmit
transmit
ential voltage to operate with transformer coupled loads
3 3 MANCHESTER DECODER
The decoder consists of a differential input circuitry and a
digital phase-locked loop to separate Manchester encoded
data stream into clock signals and NRZ data The differen-
tial input should be externally terminated if the standard
78X transceiver drop cable is used Two 39X resistors con-
nected in series and one optional common mode bypass
capacitor would accomplish this A squelch circuit at the
input rejects signals with pulse widths less than 8 ns (nega-
tive going) or with levels less than
negative than
30 ns are always decoded This prevents noise at the input
from falsely triggering the decoder in the absence of a valid
4 0 Connection Diagram
Refer to the Oscillator section
b
b
in the idle state With SEL high transmit
are equal in the idle state providing zero differ-
b
300 mV and with a duration greater than
g
) The transmit enable and transmit data
a
is positive with respect to
b
175 mV Signals more
(Continued)
See NS Package Number N24C
Order Number DP8391N
a
and
FIGURE 3
Top View
3
Figures 7 8 and 9 illustrate the receive timing
signal Once the input exceeds the squelch requirements
carrier sense (CRS) is asserted Receive data (RXD) and
receive clock (RXC) become available typically within 6 bit
times At this point the digital phase-locked loop has locked
to the incoming signal The DP8391 decodes a data frame
with up to
The decoder detects the end of a frame when the normal
mid-bit transition on the differential input ceases Within one
and a half bit times after the last bit carrier sense is de-as-
serted Receive clock stays active for five more bit times
before it goes low and remains low until the next frame
3 4 COLLISION TRANSLATOR
The Ethernet transceiver detects collisions on the coax ca-
ble and generates a 10 MHz signal on the transceiver cable
The SNI’s collision translator asserts the collision detect
output (COL) to the DP8390 controller when a 10 MHz sig-
nal is present at the collision inputs The controller uses this
signal to back off transmission and recycle itself The colli-
sion detect output is de-asserted within 350 ns after the 10
MHz input signal disappears
The collision differential inputs (
nated in exactly the same way as the receive inputs The
collision input also has a squelch circuit that rejects signals
with pulse widths less than 8 ns (negative going) or with
levels less than
timing
3 5 LOOPBACK FUNCTIONS
Logic high at loopback input (LBK) causes the SNI to route
serial data from the transmit data input through its encoder
returning it through the phase-locked-loop decoder to re-
ceive data output In loopback mode the transmit driver is in
idle state and the receive input circuitry is disabled
g
20 ns of jitter correctly
b
175 mV Figure 10 illustrates the collision
a
and
b
) should be termi-
TL F 6758 – 4