ns32491 National Semiconductor Corporation, ns32491 Datasheet

ns32491

Manufacturer Part Number

ns32491

Description

Serial Network Interface

Manufacturer

National Semiconductor Corporation

Datasheet

1.NS32491.pdf (10 pages)

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C 1995 National Semiconductor Corporation

DP8391 NS32491 Serial Network Interface

General Description

The DP8391 Serial Network Interface (SNI) provides the

Manchester data encoding and decoding functions for

IEEE 802 3 Ethernet Cheapernet type local area networks

The SNI interfaces the DP8390 Network Interface Controller

(NIC) to the Ethernet transceiver cable When transmitting

the SNI converts non-return-to-zero (NRZ) data from the

controller and clock pulses into Manchester encoding and

sends the converted data differentially to the transceiver

The opposite process occurs on the receive path where a

digital phase-locked loop decodes 10 Mbit s signals with as

much as

The DP8391 SNI is a functionally complete Manchester en-

coder decoder including ECL like balanced driver and re-

ceivers on board crystal oscillator collision signal transla-

tor and a diagnostic loopback circuit

The SNI is part of a three chip set that implements the com-

plete IEEE compatible network node electronics as shown

below The other two chips are the DP8392 Coax Transceiv-

er Interface (CTI) and the DP8390 Network Interface Con-

troller (NIC)

Incorporated into the CTI are the transceiver collision and

jabber functions The Media Access Protocol and the buffer

management tasks are performed by the NIC There is an

isolation requirement on signal and power lines between the

CTI and the SNI This is usually accomplished by using a set

of miniature pulse transformers that come in a 16-pin plastic

DIP for signal lines Power isolation however is done by

using a DC to DC converter

1 0 System Diagram

20 ns of jitter

IEEE 802 3 Compatible Ethernet Cheapernet Local Area Network Chip Set

TL F 6758

Features

Table of Contents

1 0 System Diagram

2 0 Block Diagram

3 0 Functional Description

3 1

3 2

3 3

3 4

3 5

4 0 Connection Digram

5 0 Pin Description

6 0 Absolute Maximum Ratings

7 0 Electrical Characteristics

8 0 Switching Characteristics

9 0 Timing and Load Diagrams

10 0 Physical Dimensions

Compatible with Ethernet II IEEE 802 3 10base5 and

10base2 (Cheapernet)

10 Mb s Manchester encoding decoding with receive

clock recovery

Patented digital phase locked loop (DPLL) decoder re-

quires no precision external components

Decodes Manchester data with up to

Loopback capability for diagnostics

Externally selectable half or full step modes of opera-

tion at transmit output

Squelch circuits at the receive and collision inputs re-

ject noise

High voltage protection at transceiver interface (16V)

TTL MOS compatible controller interface

Connects directly to the transceiver (AUI) cable

Oscillator

Encoder

Decoder

Collision Translator

Loopback

RRD-B30M115 Printed in U S A

20 ns of jitter

TL F 6758 – 1

July 1986

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ns32491 Summary of contents

Page 1

... DP8391 NS32491 Serial Network Interface General Description The DP8391 Serial Network Interface (SNI) provides the Manchester data encoding and decoding functions for IEEE 802 3 Ethernet Cheapernet type local area networks The SNI interfaces the DP8390 Network Interface Controller (NIC) to the Ethernet transceiver cable When transmitting ...

Page 2

Block Diagram 3 0 Functional Description The SNI consists of five main logical blocks a) the oscillator generates the 10 MHz transmit clock sig- nal for system timing b) the Manchester encoder and differential output driver accepts NRZ ...

Page 3

Functional Description mains high transmit data (TXD) is encoded out to the trans- mit-driver pair ( The transmit enable and transmit data inputs must meet the setup and hold time requirements with respect to the rising ...

Page 4

Pin Descriptions Pin No Name COL O 2 RXD O 3 CRS O 4 RXC O 5 SEL I 6 GND 7 LBK TXD I 11 TXC ...

Page 5

Absolute Maximum Ratings Supply Voltage ( Input Voltage (TTL) Input Voltage (differential) Output Voltage (differential) Output Current (differential) Storage Temperature Lead Temperature (soldering 10 sec) Package Power Rating (PC Board Mounted) Derate Linearly ...

Page 6

Switching Characteristics Symbol Parameter RECEIVE SPECIFICATION t Receive Clock Duty Cycle at 50% (10 MHz) RCd t Receive Clock Rise Time (20% to 80%) RCr t Receive Clock Fall Time (80% to 20%) RCf t Receive Data Rise ...

Page 7

Timing and Load Diagrams FIGURE 5 Transmit Timing - End of Transmission (last bit FIGURE 6 Transmit Timing - End of Transmission (last bit (Continued 6758 – 6758 ...

Page 8

Timing and Load Diagrams FIGURE 7 Receive Timing - Start of Packet FIGURE 8 Receive Timing - End of Packet (last bit (Continued 6758 – 6758 – 9 ...

Page 9

Timing and Load Diagrams FIGURE 9 Receive Timing - End of Packet (last bit 27 mH transformer is used for testing purposes 100 mH transformers (Valor LT1101 or Pulse Engineering 64103) are recommended for application use (Continued) e ...

Page 10

Physical Dimensions inches (millimeters) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein ...

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