dp83251 National Semiconductor Corporation, dp83251 Datasheet - Page 38

• Manufacturer Part Number: dp83251
• Description: Player Device Fddi Physical Layer Controller
• Manufacturer: National Semiconductor Corporation

5 0 Registers
NOISE THRESHOLD REGISTER (NTR)
The Noise Threshold Register contains the start value for the Noise Counter This counter may be used in conjunction with the
Noise Prescale Counter for counting the Noise events Definiton of Noise event is explained in detail in Section 8 2 The Noise
Counter decrements once every 80 ns if the noise Prescale counter is zero and there is a noise event As a result the internal
noise counter takes
to reach zero in the event of continuous Noise event
The threshold values for the Noise Counter and Noise Prescale Counter are simultaneously loaded into both counters if one of
the following conditions is true
(1) Both the Noise Counter and Noise Prescale Counter reach zero and the current Line State is either Noise Line State Active
or
(2) The current Line State is either Halt Line State Idle Line State Master Line State Quiet Line State or No Signal Detect
or
(3) The Noise Threshold Register or Noise Prescale Threshold Register goes through a Control Bus Interface write cycle
In addition the value of the Noise Prescale Threshold register is loaded into the Noise Prescale Counter if the Noise Prescale
Counter reaches zero
The Noise Counter and Noise Prescale Counter will continue to count without resetting or reloading the threshold values if a
Line State change occurs and the new line state is either Noise Line State Active Line State or Line State Unknown
When both the Noise Threshold Counter and Noise Counter both reach zero the Noise Threshold bit of the Receive Condition
Register A will be set
ACCESS RULES
D0
D1 – 5
D6
D7
Line State or Line State Unknown
D7
NT7
ADDRESS
Bit
0Dh
D6
NT6
(Continued)
NT0
NT1 – 5
NT6
RES
Symbol
Always
READ
D5
NT5
D4
NT4
WRITE
Always
((NPTR
NOISE THRESHOLD BIT
for the Noise Counter
NOISE THRESHOLD BIT
Noise Counter
NOISE THRESHOLD BIT
for the Noise Counter
RESERVED Reserved for future use
Note Users are discouraged from using this bit Write data is ignored since the reserved
bit is permanently set to 0
a
1) x (NTR
D3
NT3
38
a
1)) x 80 ns
D2
NT2
k
k
k
0
1 – 5
6
l
l
Least significant bit (LSB) of the start value
Description
l
Most significant bit (MSB) of the start value
Intermediate bits of start value for the
D1
NT1
D0
NT0