dp83251 National Semiconductor Corporation, dp83251 Datasheet - Page 25

• Manufacturer Part Number: dp83251
• Description: Player Device Fddi Physical Layer Controller
• Manufacturer: National Semiconductor Corporation

5 0 Registers
INTERRUPT CONDITION REGISTER (ICR) (Continued)
Bit
D4
D5
D6
D7
Symbol
LEMT
RCA
RCB
UDI
(Continued)
LINK ERROR MONITOR THRESHOLD This bit is set to 1 when the internal 8-bit Link Error Monitor
Counter reaches zero It will remain set until cleared by software
During the reset process (i e RST
Link Error Monitor Counter is initialized to zero
RECEIVE CONDITION A This bit is set to 1 when
(1) One or more bits in the Receive Condition Register A (RCRA) is set to 1 and
(2) The corresponding mask bits in the Receive Condition Mask Register A (RCMRA) are also set to 1
In order to clear (i e set to 0) the Receive Condition A bit the bits within the Receive Condition Register
A that are set to 1 must first be either cleared or masked
RECEIVE CONDITION B This bit is set to 1 when
(1) One or more bits in the Receive Condition Register B (RCRB) is set to 1 and
(2) The corresponding mask bits in the Receive Condition Mask Register B (RCMRB) are also set to 1
In order to clear (i e set to 0) the Receive Condition B bit the bits within the Receive Condition Register
B that are set to 1 must first be either cleared or masked
USER DEFINABLE INTERRUPT This bit is set to 1 when one or both of the Sense Bits (SB0 or SB1) in
the User Definable Register (UDR) is set to 1
In order to clear (i e set to 0) the User Definable Interrupt Bit both Sense Bits must be set to 0
e
GND) the Link Error Monitor Threshold bit is set to 1 because the
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Description