dp83901a National Semiconductor Corporation, dp83901a Datasheet - Page 61

• Manufacturer Part Number: dp83901a
• Description: Serial Network Interface Controller
• Manufacturer: National Semiconductor Corporation

15 0 Switching Characteristics
TRANSMIT SPECIFICATIONS (End of Packet)
Note 1 The RESET pulse requires the BSCK and TXC be stable On power up RESET should not be raised until BSCK and TXC have become stable Several
registers are affected by RESET Consult the register descriptions for details
Note 2 The slower of BSCK or TXC clocks will determine the minimum time for the RESET signal to be low TXC is X1 divided by 2
16 0 AC Timing Test Conditions
All specifications are valid only if the mandatory isolation is
employed and all differential signals are taken to be at the
AUI side of the pulse transformer
Input Pulse Levels (TTL CMOS)
Input Rise and Fall Times (TTL CMOS)
Input and Output Reference Levles (TTL CMOS)
Input Pulse Levels (Diff )
Input and Output
TRI-STATE Reference Levels
Output Load (See Figure Below)
Reference Levels (Diff )
Symbol
rstw
Symbol
t
t
TOH
TOI
If BSCK
If TXC
k
k
BSCK then RESET
TXC then RESET
Reset Pulse Width (Note 1)
Transmit Output High before Idle (Half Step)
Transmit Output Idle Time to
Parameter
e
e
8
8
c
c
b
BSCK
TXC
350 mV to
Parameter
Float (DV)
Transmit Timing (End of Packet)
the Differential
50% Point of
GND to 3 0V
b
1315 mV
AC Specs DP83901A Note All Timing is Preliminary (Continued)
g
g
40 mV(Half Step)
Reset Timing
1 3V
0 5V
5 ns
Min
8
61
Note 1 50 pF includes scope and jig capacitance
Note 2 S1
Max
S1
S1
S1
active low to High Impedance measurements
S1
active high to High Impedance measurements
e
e
e
e
e
V
GND for V
V
GND for High Impedance to active high and
Open for timing tests for push pull outputs
CC
CC
for V
for High Impedance to active low and
Min
200
OL
BSCK Cycles or TXC Cycles (Note 2)
OH
test
test
8000
Max
Units
TL F 10469 – 47
TL F 10469 – 48
TL F 10469 – 45
Units
ns
ns