mpc5561 Freescale Semiconductor, Inc, mpc5561 Datasheet - Page 9

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mpc5561

Manufacturer Part Number
mpc5561
Description
Mpc5561 Power Architecture Tm 32-bit Mcu For Automotive
Manufacturer
Freescale Semiconductor, Inc
Datasheet
2.6.6
2.6.7
2.6.8
2.6.9
Freescale Semiconductor
1.8
324 BGA: 16-bit data bus, 24-bit address bus is default ADDR[8:31], but configurable to 26-bit
address bus.
Memory controller with support for various memory types
— Non-burst SDR flash and SRAM
— Asynchronous/legacy flash and SRAM
— Most standard memories used with the MPC5xx family
Configurable bus speed modes
— 50% of system frequency
— 25% of system frequency
Support for external master accesses to internal addresses (master/slave system only)
Burst support
Bus monitor
— User selectable
— Programmable timeout period (with eight external bus clock resolution)
Four chip selects: CS[0:3] multiplexed with ADDR[8:11]
Two write/byte enable (WE/BE[0:1]) signals in the 324-pin package
Configurable wait states (via chip selects)
Optional automatic CLKOUT gating to save power and reduce EMI
Compatible with MPC5xx external bus (with some limitations):
Selectable drive strengths; 10 pF, 20 pF, 30 pF, 50 pF
Centralized GPIO control of bus pins:
— 324 BGA package: 150 pins
Centralized pad control on a per-pin basis
System reset monitoring and generation
External interrupt inputs, filtering and control
Configurable error-correcting codes (ECC) reporting for internal SRAM and flash memories
1 MB burst flash memory
128 KB × 64-bit configuration
Censorship protection scheme to prevent flash content visibility
3.3 V nominal I/O voltage
External Bus Interface (EBI)
System Integration Unit (SIU)
Error Correction Status Module (ECSM)
On-chip Flash Memory
MPC5561 Microcontroller Product Brief, Rev. 1
Features
9

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