mpc8640 Freescale Semiconductor, Inc, mpc8640 Datasheet - Page 45

• Manufacturer Part Number: mpc8640
• Description: Integrated Host Processor
• Manufacturer: Freescale Semiconductor, Inc

Figure 26
Table 42
bypassed.
Freescale Semiconductor
Local bus cycle time
Local bus duty cycle
Internal launch/capture clock to LCLK delay
Input setup to local bus clock (except LGTA/LUPWAIT)
LGTA/LUPWAIT input setup to local bus clock
Input hold from local bus clock (except LGTA/LUPWAIT)
LA[27:31]/LBCTL/LBCKE/LOE/
LSDA10/LSDWE/LSDRAS/
describes the general timing parameters of the local bus interface at OV
shows the local bus signals with PLL enabled.
Output (Address) Signal:
LSDCAS/LSDDQM[0:3]
Output (Data) Signals:
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
PLL bypass mode is recommended when LBIU frequency is at or below
83 MHz. When LBIU operates above 83 MHz, LBIU PLL is recommended
to be enabled.
LAD[0:31]/LDP[0:3]
LAD[0:31]/LDP[0:3]
Output Signals:
Input Signals:
Input Signal:
Parameter
LSYNC_IN
LUPWAIT
LAD[0:31]
Table 42. Local Bus Timing Parameters—PLL Bypassed
LGTA
LALE
Figure 26. Local Bus Signals (PLL Enabled)
t
t
LBKHOV1
LBKHOV2
t
LBKHOV3
t
LBKHOV4
NOTE
t
t
t
t
t
LBIVKH1
LBIVKH2
LBKHOX1
LBKHOX2
LBKHOX2
t
t
t
t
Symbol
LBKHOZ1
LBKHOZ2
LBKHOZ2
LBKH/
t
t
t
t
LBIVKH1
LBIXKH1
LBKHKT
LBIVKL2
t
t
LBK
LBOTOT
t
LBK
1
–1.8
Min
2.3
5.7
5.6
12
45
t
t
LBIXKH1
LBIXKH2
Max
3.9
55
—
—
—
—
DD
= 3.3 V with PLL
Unit
ns
ns
ns
ns
ns
%
Local Bus
Notes
4, 5
4, 5
4, 5
—
2
8
45