mpc8640 Freescale Semiconductor, Inc, mpc8640 Datasheet - Page 106

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mpc8640

Manufacturer Part Number
mpc8640
Description
Integrated Host Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Clocking
Note that there is no default for this PLL ratio; these signals must be pulled to the desired values. Also note
that the DDR data rate is the determining factor in selecting the MPX bus frequency because the MPX
frequency must equal the DDR data rate.
18.3
Table 69
by the binary value of LDP[0:3], LA[27](cfg_core_pll[0:4] - reset config name) at power up, as shown in
Table
18.4
This section discusses the frequency options for the MPC8640.
106
69.
Binary value on LA[28:31] at power up
describes the clock ratio between the platform and the e600 core clock. This ratio is determined
e600 to MPX clock PLL Ratio
Frequency Options
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
LDP[0:3], LA[27] Signals
Binary Value of
Table 69. e600 Core to MPX Clock Ratio
LA[28:31] Signals
Binary Value of
01000
01100
10000
11100
10100
01110
Table 68. MPX:SYSCLK Ratio
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
e600 core: MPX Clock Ratio
MPX:SYSCLK Ratio
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2:1
3:1
4:1
5:1
6:1
8:1
2.5:1
2:1
3:1
Freescale Semiconductor

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