mc68hc711d3 Freescale Semiconductor, Inc, mc68hc711d3 Datasheet - Page 135
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mc68hc711d3
Manufacturer Part Number
mc68hc711d3
Description
M Hc11 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC711D3.pdf
(138 pages)
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B.2.6 Serial Peripheral Interface Timing
Freescale Semiconductor
Num
1. V
2. Signal production depends on software.
3. Assumes 100 pF load on all SPI pins.
10
11
12
13
1
2
3
4
5
6
7
8
9
otherwise noted.
DD
Operating frequency
Cycle time
Enable lead time
Enable lag time
Clock (SCK) high time
Clock (SCK) low time
Data setup time (inputs)
Data hold time (inputs)
Access time (time to data active from high-impedance state)
Disable time (hold time to high-impedance state)
Data valid (after enable edge)
Rise time (20% V
Fall time (70% V
Data hold time (outputs) (after enable edge)
= 3.0 Vdc to 5.5 Vdc, V
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Slave
Slave
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
(2)
(2)
DD
DD
to 20% V
to 70% V
Characteristic
SS
= 0 Vdc, T
DD
(3)
DD
, C
, C
L
L
= 200 pF)
(1)
MC68HC711D3 Data Sheet, Rev. 2.1
= 200 pF)
A
= T
L
to T
H
. All timing is shown with respect to 20% V
t
t
t
t
Symbol
w(SCKH)m
w(SCKL)m
w(SCKH)s
w(SCKL)s
t
t
t
t
t
lead(m)
f
CYC(s)
t
t
lead(s)
f
cyc(m)
t
lag(m)
t
op(m)
su(m)
lag(s)
t
op(s)
su(s)
t
h(m)
t
t
h(s)
t
t
v(s)
t
t
t
dis
ho
rm
fm
rs
fs
a
1000
Min
500
500
680
380
680
380
100
100
100
100
2.0
dc
dc
—
—
—
—
—
—
—
—
0
0
MC68L11D0 Electrical Characteristics
1.0 MHz
Max
120
240
240
100
100
0.5
1.0
2.0
2.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DD
and 70% V
Min
500
250
250
340
190
340
190
100
100
100
100
2.0
dc
dc
—
—
—
—
—
—
—
—
0
0
2.0 MHz
Max
120
240
240
100
100
0.5
2.0
2.0
2.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DD
, unless
Unit
MHz
t
f
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
µs
cyc
op
135