mc68hc708mp16 Freescale Semiconductor, Inc, mc68hc708mp16 Datasheet - Page 115
mc68hc708mp16
Manufacturer Part Number
mc68hc708mp16
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC708MP16.pdf
(398 pages)
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8.5.4 PLL Analog Power Pin (V
8.5.5 Oscillator Enable Signal (SIMOSCEN)
8.5.6 Crystal Output Frequency Signal (CGMXCLK)
8.5.7 CGM Base Clock Output (CGMOUT)
MC68HC708MP16
Freescale Semiconductor
NOTE:
NOTE:
—
Rev. 3.1
To prevent noise problems, C
CGMXFC pin as possible, with minimum routing distances and no
routing of other signals across the C
V
V
Route V
capacitors as close as possible to the package.
The SIMOSCEN signal comes from the system integration module (SIM)
and enables the oscillator and PLL.
CGMXCLK is the crystal oscillator output signal. It runs at the full speed
of the crystal (f
Figure 8-3
OSC2 and may not represent the actual circuitry. The duty cycle of
CGMXCLK is unknown and may depend on the crystal and other
external factors. Also, the frequency and amplitude of CGMXCLK can be
unstable at start-up.
CGMOUT is the clock output of the CGM. This signal goes to the SIM,
which generates the MCU clocks. CGMOUT is a 50% duty cycle clock
running at twice the bus frequency. CGMOUT is software programmable
to be either the oscillator output, CGMXCLK, divided by two or the VCO
clock, CGMVCLK, divided by two.
DDA
DDA
is a power pin used by the analog portions of the PLL. Connect the
pin to the same voltage potential as the V
DDA
DDA
Clock Generator Module (CGM)
shows only the logical relation of CGMXCLK to OSC1 and
)
carefully for maximum noise immunity and place bypass
XCLK
) and comes directly from the crystal oscillator circuit.
F
should be placed as close to the
F
connection.
Clock Generator Module (CGM)
DD
pin.
Technical Data
115
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