mc68hc05p18a Freescale Semiconductor, Inc, mc68hc05p18a Datasheet - Page 53

• Manufacturer Part Number: mc68hc05p18a
• Description: Mc68hc05p18a Hcmos Microcontroller Unit
• Manufacturer: Freescale Semiconductor, Inc

6.4.1.2 Halt Mode
6.4.2 WAIT Instruction
MC68HC05P18A
NOTE:
NOTE:
Execution of the STOP instruction with the conversion to halt places the
MCU in this low-power mode. Halt mode consumes the same amount of
power as wait mode.
Both halt and wait modes consume more power than stop mode.
In halt mode the PH2 clock is halted, suspending all processor and
internal bus activity. Internal timer clocks remain active, permitting
interrupts to be generated from the 16-bit timer or a reset to be
generated from the COP watchdog timer. Execution of the STOP
instruction automatically clears the I bit in the condition code register,
enabling the IRQ external interrupt. All other registers, memory, and
input/output lines remain in their previous states.
If the 16-bit timer interrupt is enabled, it causes the processor to exit halt
mode and resume normal operation. Halt mode also can be exited when
an IRQ external interrupt or external RESET occurs. When exiting halt
mode, the PH2 clock resumes after a delay of one to 4064 PH2 clock
cycles. This varied delay time is the result of the halt mode exit circuitry
testing the oscillator stabilization delay timer (a feature of stop mode)
which has been free-running (a feature of wait mode).
Halt mode is not intended for normal use. This feature is provided to
keep the COP watchdog timer active in the event a STOP instruction is
inadvertently executed.
The WAIT instruction places the MCU in a low-power mode, which
consumes more power than stop mode. In wait mode, the PH2 clock is
halted, suspending all processor and internal bus activity. Internal timer
clocks remain active, permitting interrupts to be generated from the 16-
bit timer and reset to be generated from the COP watchdog timer.
Execution of the WAIT instruction automatically clears the I bit in the
condition code register, enabling the IRQ external interrupt. All other
registers, memory, and input/output lines remain in their previous state.
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Operating Modes
Low-Power Modes
Operating Modes
Technical Data