mc68hc908gr8b Freescale Semiconductor, Inc, mc68hc908gr8b Datasheet - Page 156

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mc68hc908gr8b

Manufacturer Part Number
mc68hc908gr8b
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
System Integration Module (SIM)
The SIM is responsible for:
Table 14-1
156
Addr.
$FE00
$FE01
$FE03
$FE04
$FE05
$FE06
Bus clock generation and control for CPU and peripherals:
Master reset control, including power-on reset (POR) and computer operating properly (COP)
timeout
Interrupt arbitration
SIM Break Status Register
SIM Reset Status Register
Stop/wait/reset/break entry and recovery
Internal clock control
SIM Break Flag Control
Signal Name
Register Name
shows the internal signal names used in this section.
CGMXCLK
CGMVCLK
CGMOUT
PORRST
Register (SBFCR)
IRST
R/W
IDB
Register 1 (INT1)
Register 2 (INT2)
Register 3 (INT3)
IAB
Interrupt Status
Interrupt Status
Interrupt Status
See page 169.
See page 170.
See page 171.
See page 165.
See page 166.
See page 166.
(SRSR)
(SBSR)
Buffered version of OSC1 from clock generator module (CGM)
PLL output
PLL-based or OSC1-based clock output from CGM module
(Bus clock = CGMOUT divided by two)
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
Read/write signal
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
POR:
Figure 14-2. SIM I/O Register Summary
Table 14-1. Signal Name Conventions
1. Writing a 0 clears SBSW.
BCFE
MC68HC908GR8B Data Sheet, Rev. 3.0
Bit 7
POR
IF14
IF6
R
R
R
R
0
1
0
0
0
0
0
= Unimplemented
IF13
PIN
IF5
R
R
R
R
R
6
0
0
0
0
0
0
COP
IF12
IF4
R
R
R
R
R
5
0
0
0
0
0
0
Description
ILOP
IF11
IF3
R
R
R
R
R
R
4
0
0
0
0
0
0
= Reserved
ILAD
IF10
IF2
R
R
R
R
R
3
0
0
0
0
0
0
MODRST
IF1
IF9
R
R
R
R
R
2
0
0
0
0
0
0
Freescale Semiconductor
Note
SBSW
IF16
LVI
IF8
R
R
R
R
1
0
0
0
0
0
0
(1)
Bit 0
IF15
IF7
R
R
R
R
R
0
0
0
0
0
0
0

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