z86e54 ZiLOG Semiconductor, z86e54 Datasheet - Page 43

• Manufacturer Part Number: z86e54
• Description: Z8 512 Byte Otp Mcu
• Manufacturer: ZiLOG Semiconductor

PS020102-1003
Watch-Dog Timer (WDT)
Note:
The Watch-Dog Timer is enabled by instruction WDT. When the WDT is enabled,
it cannot be stopped by the instruction. With the WDT instruction, the WDT is
refreshed when it is enabled within every 1 T
resets itself, The WDT instruction affects the flags accordingly; Z = 1, S = 0, V = 0.
Op Code WDT (5Fh)
The first time Op Code 5Fh is executed, the WDT is enabled; subsequent execu-
tion clears the WDT counter. This clearing of the counter must be performed at
least every T
erated reset is the same as a power-on reset of T
The software enabled WDT does not run in STOP mode, only the hardware
enabled permanent WDT runs in STOP Mode and HALT Mode (without the WDH
instruction).
Op Code WDH (4Fh)
When this instruction is executed it enables the WDT during HALT. If not, the WDT
stops when entering HALT. This instruction does not clear the counters – it just
makes it possible to operate the WDT during HALT mode. A WDH instruction exe-
cuted without executing WDT (5Fh) yields no effect. If the hardware enabled per-
manent WDT is enabled, then the WDT runs in HALT Mode without the use of the
WDH instruction.
Permanent WDT
Selecting the hardware-enabled Permanent WDT option bit automatically enables
the WDT upon exiting reset. The permanent WDT always runs in HALT mode and
STOP mode, and it cannot be disabled.
WDT = 5Fh
On the CCP emulator, a software workaround must be used to
enable the software in HALT Mode/STOP Mode or hardware-
enabled WDT. This workaround follows.
WDT
POP RP
; otherwise, the WDT times out and generates a reset. The gen-
X= 0 for STANDARD Mode
WDT
PQR
period; otherwise, the controller
, plus 18 crystal clock cycles.
Z8
®
512 Byte OTP MCU
Z86E54
37