ml67q5200 ETC-unknow, ml67q5200 Datasheet - Page 3

• Manufacturer Part Number: ml67q5200
• Description: Digital Audio Controller
• Manufacturer: ETC-unknow

Functional Description
High-Performance ARM-based CPU
• Instructions: ARM (32-bit length) and Thumb (16-bit length) can be
• General register bank: 31 x 32 bits
• Built-in barrel shifter: ALU and barrel shift operations can be executed
• Multiplier: 32 bits x 8 bits (Modified Booth Algorithm)
• Cache: 8 Kbyte, 4-way copy back unified cache
• Built-in debug function: JTAG interface
DSP Module
The Teak DSP decodes MP3/WMA digital audio data. Also encodes/decodes
voice data as Oki ADPCM.
• X-RAM: 16 Kwords (32 Kbytes)
• Y-RAM: 16Kwords (32 Kbytes)
• Z-RAM: 16 Kwords (32 Kbytes)
• P-program RAM: 32 Kwords (64 Kbytes)
• Built-in debug function: JTAG interface
• MP3 decoder:
• WMA decoder:
• MP3 encoder:
USB Control
The USB controller is compliant with the USB specification (version 1.1) and
can transfer data at 12 Mbps.
The controller has 6 types of endpoints for control/bulk/isochronous/interrupt
transfers.
NAND Flash Memory Control
The NAND Flash memory circuit automatically reads data from and writes
data to an external 528-byte NAND Flash Memory.
Also includes an ECC circuit that detects and corrects multiple-bit data errors.
DMA Control
The 4-channel DMA controller transfers data between:
• Memory and memory
• I/O and memory
• I/O and I/O
External Memory Control
The external memory controller provides access to externally-connected
devices such as ROM (FLASH), SRAM, SDRAM and I/O.
Connect 16-bit data bus length device and byte unit access device which have
byte select function.
Power Management
The HALT, STOP, and SLEEP functions are supported as power-save functions.
Switching the CPU clock to the 1/2, 1/4, or 1/8 of the main clock enables
operation in a low power consumption mode.
• HALT mode: Stops the ARM7TDMI and AHB/APB bus.
mixed.
by one instruction.
- MPEG-1 layer3, MPEG-2 layer3, MPEG-2.5
- Bit rate: 64 kbps, 96 kbps, 128 kbps, 160 kbps, 192 kbps
- Sampling rate: 32 kHz, 44.1 kHz, 48 kHz
- 64 kbps/96 kbps/128 kbps @ 44.1kHz
• STOP mode: Stops the DSP module clock first, then the clock for the
• SLEEP mode: Stops the power supply to the DSP module first, then
entire device.
stops the clock for the entire device.
ML675200/ML67Q5200
Oki Semiconductor • 3