ade7953 Analog Devices, Inc., ade7953 Datasheet - Page 52

• Manufacturer Part Number: ade7953
• Description: Single Phase, Multifunction Metering Ic With Neutral Current Measurement Ade7953
• Manufacturer: Analog Devices, Inc.

ADE7953
I
The ADE7953 supports a fully licensed I
interface operates as a slave and uses two shared pins: SDA and
SCL. The SDA pin is a bidirectional input/output pin, and the
SCL pin is the serial clock. Both pins are shared with the SPI
and UART interfaces. The I
serial clock frequency of 400 kHz.
The two pins used for data transfer—SDA and SCL—are
configured in a wire-AND format that allows arbitration in
a multimaster system.
Communication via the I
device generating a start condition. This consists of the master
transmitting a single byte containing the address of the slave
device and the nature of the operation (read or write).
The address of the ADE7953 is 0111000X. Bit 7 in the address
byte indicates whether a read or a write is required: 0 indicates a
write, and 1 indicates a read. The communication continues as
described in the following sections until the master issues a stop
condition and the bus returns to the idle condition.
2
C INTERFACE
S
0
SLAVE ADDRESS
1 1 1 0 0 0 0
A
C
K
15
MSB OF REGISTER ADDRESS
2
C interface is initiated by the master
2
C interface operates at a maximum
8
A
C
K
2
C interface. The I
7
LSB OF REGISTER ADDRESS
0
A
C
K
2
C
23
BYTE 3 (MSB) OF REGISTER
Rev. 0 | Page 52 of 68
Figure 70. I
ACK GENERATED BY
2
C Write
ADE7953
16
I
A write operation on the ADE7953 is initiated when the master
issues a start condition, which consists of the slave address and
the read/write bit. The start condition is followed by the 16-bit
address of the target register. After each byte is received, the
ADE7953 issues an acknowledge (ACK) to the master.
As soon as the 16-bit address communication is complete, the
master sends the register data, MSB first. The length of this data
can be 8, 16, 24, or 32 bits long. After each byte of register data
is received, the ADE7953 slave issues an acknowledge (ACK).
When transmission of the final byte is complete, the master
issues a stop condition, and the bus returns to the idle condition.
The I
2
C Write Operations
A
C
K
15
2
BYTE 2 OF REGISTER
C write operation is shown in Figure 70.
8
A
C
K
7
BYTE 1 OF REGISTER
0
A
C
K
7
BYTE 0 (LSB) OF REGISTER
0
C
K
A
P