ade7169f16 Analog Devices, Inc., ade7169f16 Datasheet - Page 27

• Manufacturer Part Number: ade7169f16
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc And Lcd Driver
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Battery Switchover and Power Supply Restored
PSM Interrupt
The ADE7169F16 can be configured to generate a PSM
interrupt when the source of V
indicating battery switchover. Setting the EBSO bit in the
Power Management Interrupt Enable SFR (IPSME, 0xEC)
enables this event to generate a PSM interrupt.
The ADE7169F16 can also be configured to generate an
interrupt when the source of V
indicating that the V
event is enabled to generate a PSM interrupt by setting the
EPSR bit in the Power Management Interrupt Enable SFR
(IPSME, 0xEC).
The flags in the Power Management Interrupt Flag SFR (IPSMF,
0xF8) for these interrupts, BSOF and PSRF are set regardless of
whether the respective enable bits have been set. The battery
switchover and power supply restore event flags, BSOF and
PSRF, are latched. These events must be cleared by writing a
zero to these bits. Bit 6 in the Peripheral Configuration SFR
(PERIPH, 0xF4), VSWSOURCE, tracks the source of V
bit is set when V
connected to V
V
The ADE7169F16 can be configured to generate a PSM
interrupt when V
configurable threshold. This threshold is set in the
IEIP2 Addr. 0A9h
IPSMF Addr. 0F8h
IPSME Addr. 0ECh
SW
Monitor PSM Interrupt
BAT
SW
SW
.
is connected to V
changes magnitude by more than a
DD
power supply has been restored. This
reserved
EVDCIN
FVDCIN
FPSR
EPSR
EVSW
FVSW
: Not involved in PSM Interrupt signal chain
EPSR
ESAG
FSAG
EBSO
FBSO
FPSR
EBAT
FBAT
SW
SW
changes from V
changes from V
ADEAUTOCLR
DD
and cleared when V
FPSM
PTI
DD
BAT
to V
to V
reserved
FSAG
ESAG
SW
Figure 10: PSM Interrupt Sources
BAT
DD
. The
Rev. PrD | Page 27 of 140
,
,
SW
is
FPSM
EPSM
reserved
reserved
PSI
Temperature and Supply Delta SFR (DIFFPROG, 0xF3) –see
Supply Voltage Measurement section. Setting the EVSW bit in
the Power Management Interrupt Enable SFR (IPSME, 0xEC)
enables this event to generate a PSM interrupt.
The V
measurements take place in the background at intervals to
check the change in V
writing to the Start ADC Measurement SFR (ADCGO, 0xD8).
The EVSW flag will indicate that a V
See the Supply Voltage Measurement section for details on how
V
V
The V
measurements take place in the background at intervals to
check the change in V
level is lower than the threshold set in the Battery detection
threshold SFR (BATVTH, 0xFA) or when a new measurement
is ready in the Battery ADC value SFR (BATADC, 0xDF) - see
Battery measurement section. Setting the EBATT bit in the
Power Management Interrupt Enable SFR (IPSME, 0xEC)
enables this event to generate a PSM interrupt.
V
The V
in the Power Management Interrupt Flag SFR (IPSMF, 0xF8) is
set when the V
EVDCIN bit in the Power Management Interrupt Enable SFR
SW
BAT
DCIN
is measured.
Monitor PSM Interrupt
SW
BAT
DCIN
Monitor PSM Interrupt
TRUE?
voltage is measured using a dedicated ADC. These
voltage is measured using a dedicated ADC. These
EADE
FVSW
EVSW
voltage is monitored by a comparator. The FVDC bit
DCIN
input level is lower than 1.2 V. Setting the
Pending PSM interrupt
SW
BAT
. Conversions can also be initiated by
FBAT
EBAT
. The BATTF bit is set when the battery
ETI
SW
EPSM
measurement is ready.
EBSO
FBSO
ADE7169F16
EVDCIN
FVDCIN
ESI