ade7169f16 Analog Devices, Inc., ade7169f16 Datasheet - Page 131

• Manufacturer Part Number: ade7169f16
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc And Lcd Driver
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
whether a read or write operation is performed on the slave device. During the read operation, the master acknowledges are generated
automatically by the I2C peripheral. The master generated NACK before the end of a read operation is also generated automatically after
I2CRCT[4:0] bytes have been read from the slave. If the I2CADR register is updated during a transmission, instead of generating a STOP
at the end of the read or write operation, the master will generate a START condition and continue with the next communication.
SDA
I2C RECEIVE AND TRANSMIT FIFOS
The I2C peripheral has a four byte receive FIFO and a four byte
transmit FIFO. The buffers reduce the overhead associated with
using the I2C peripheral. Figure 87 shows the operation of the
I2C receive and transmit FIFOs.
The TX FIFO can be loaded with four bytes to be transmitted to
the slave at the beginning of a write operation. When the
transmit FIFO is empty, the I2C transmit interrupt flag will be
set and the PC will vector to the I2C interrupt vector if this
interrupt is enabled. If a new byte is not loaded into the TX
FIFO before it is needed in the transmit shift register, the
communication will stop. An error such as not receiving an
acknowledge will also cause the communication to terminate.
In case of an error during a write operation, the TX FIFO will
be flushed.
The RX FIFO allows four bytes to be read in from the slave
before the MCU has to read the data. A receive interrupt can be
generated after each byte is received or when the RX FIFO is
SCL
START BY
MASTER
A6
1
A5
SERIAL BUS ADDRESS BYTE
A4
SDA
SCL
FRAME 1
START BY
A3
MASTER
A2
A6
A1
1
A5
A0
SERIAL BUS ADDRESS BYTE
A4
R/W
ACK BY
SLAVE
FRAME 1
A3
9
A2
D7
1
D6
A1
Figure 86: I2C Write operation
Figure 85: I2C Read operation
A0
D5
DATA BYTE 1 FROM SLAVE
Rev. PrD | Page 131 of 140
R/W
D4
ACK BY
SLAVE
FRAME 2
9
D3
D7
1
D2
D6
full. If the peripheral is reading from a slave address, the
communication will stop once the number of received bytes
equals the number set in the I2CRCT[4:0] bits. An error such as
not receiving an acknowledge will also cause the
communication to terminate.
Code to fill TX FIFO:
Code to fill TX FIFO:
4 Byte FIFO
D1
D5
MOV I2CTX, TXDATA1
MOV I2CTX, TXDATA1
MOV I2CTX, TXDATA2
MOV I2CTX, TXDATA2
MOV I2CTX, TXDATA3
MOV I2CTX, TXDATA3
MOV I2CTX, TXDATA4
TRANSMIT SHIFT REGISTER
TRANSMIT SHIFT REGISTER
DATA BYTE 1 FROM MASTER
D0
MASTER
ACK BY
D4
9
TXDATA2
TXDATA2
TXDATA4
TXDATA3
TXDATA3
TXDATA1
TXDATA1
FRAME 2
I2CTX
I2CTX
D3
D2
D7
Figure 87: I2C FIFO operation
1
D1
D6
D0
ACK BY
D5
SLAVE
Code to read RX FIFO:
4 Byte FIFO
DATA BYTE N FROM SLAVE
9
MOV A, I2CRX
MOV A, I2CRX
MOV A, I2CRX
MOV A, I2CRX
D4
RECEIVE SHIFT REGISTER
FRAME N+1
STOP BY
D3
MASTER
RXDATA3
RXDATA1
RXDATA2
RXDATA4
I2CRX
D2
ADE7169F16
D1
; Result: A=RXDATA1
; Result: A=RXDATA2
; Result: A=RXDATA3
; Result: A=RXDATA4
D0
NACK BY
MASTER
9
STOP BY
MASTER