ade7166 Analog Devices, Inc., ade7166 Datasheet - Page 117

• Manufacturer Part Number: ade7166
• Description: Single-phase Energy Measurement Ic With 8052 Mcu, Rtc, And Lcd Driver
• Manufacturer: Analog Devices, Inc.

Table 120. RTC Configuration SFR (TIMECON, 0xA1)
Bit
7
6
5 to 4
3
2
1
0
Table 121. Hundredths of a Second Counter SFR (HTHSEC, 0xA2)
Bit
7 to 0
Table 122. Seconds Counter SFR (SEC, 0xA3)
Bit
7 to 0
Table 123. Minutes Counter SFR (MIN, 0xA4)
Bit
7 to 0
Table 124. Hours Counter SFR (HOUR, 0xA5)
Bit
7 to 0
Mnemonic
MIDNIGHT
TFH
ITS[1:0]
SIT
ALARM
ITEN
Reserved
Mnemonic
HTHSEC
Mnemonic
SEC
Mnemonic
MIN
Mnemonic
HOUR
Default
0
0
0
0
0
1
Default
Default
0
Default
0
0
0
Default
0
Description
Midnight Flag. This bit is set when the RTC rolls over to 00:00:00:00. It can be cleared by the user to
indicate that the midnight event has been serviced. In twenty-four hour mode, the midnight flag is
raised once a day at midnight. When this interrupt is used for wake-up from PSM2 to PSM1, the RTC
interrupt must be serviced and the flag cleared to be allowed to enter PSM2.
Twenty-Four Hour Mode. This bit is retained during a watchdog reset or an external reset. It is reset after
a power-on reset (POR).
TFH
0
1
Interval Timer Timebase Selection.
ITS[1:0]
00
01
10
11
Interval Timer 1 Alarm.
SIT
0
1
Interval Timer Alarm Flag. This bit is set when the configured time interval has elapsed. It can be cleared
by the user to indicate that the alarm event has been serviced. This bit cannot be set to 1 by user code.
Interval Timer Enable.
ITEN
0
1
This bit must be left set for proper operation.
Description
This counter updates every 1/128 second, referenced from the calibrated 32.768 kHz clock. It overflows
from 127 to 00, incrementing the seconds counter (SEC). This register is retained during a watchdog
reset or an external reset. It is reset after a POR.
Description
This counter updates every second, referenced from the calibrated 32.768 kHz clock. It overflows from 59 to
00, incrementing the minutes counter (MIN). This register is retained during a watchdog reset or an
external reset. It is reset after a POR.
Description
This counter updates every minute, referenced from the calibrated 32.768 kHz clock. It overflows from 59 to
00, incrementing the hours counter, HOUR. This register is retained during a watchdog reset or an
external reset. It is reset after a POR.
Description
This counter updates every hour, referenced from the calibrated 32.768 kHz clock. If the TFH bit in the
RTC Configuration SFR (TIMECON, 0xA1) is set, the HOUR SFR overflows from 23 to 00, setting the
MIDNIGHT bit and creating a pending RTC interrupt. If the TFH bit is cleared, the HOUR SFR overflows from
255 to 00, setting the MIDNIGHT bit and creating a pending RTC interrupt. This register is retained during
a watchdog reset or an external reset. It is reset after a POR.
Result
256-Hour Mode. The HOUR register rolls over from 255 to 0.
24-Hour Mode. The HOUR register rolls over from 23 to 0.
Result (Time Base)
1/128 sec.
Second.
Minute.
Hour.
Result
The ALARM flag is set after INTVAL counts and then another interval count starts.
The ALARM flag is set after one time interval.
Result
The interval timer is disabled. The 8-bit interval timer counter is reset.
Set this bit to enable the interval timer. The RTCEN bit must also be set to enable the
interval timer.
Rev. A | Page 117 of 144
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