mm908e621 Freescale Semiconductor, Inc, mm908e621 Datasheet - Page 43

• Manufacturer Part Number: mm908e621
• Description: Integrated Quad Half-bridge And Triple High-side With Embedded Mcu And Lin For High End Mirror
• Manufacturer: Freescale Semiconductor, Inc

SRS0-1 — LIN Slew rate Select Bits
appropriate LIN slew rate for different Baudrate
configurations.
Reset clears the SRS1:0 bits.
programming via the LIN and are not intended for use in the
application.
System Status Register (SYSSTAT)
LINCL — LIN Current Limitation Bit
current limitation region. Due to excessive power dissipation
in the transmitter, the driver will be automatically turned off
after a certain time.
HTIF— Overtemperature Status Bit
Flag register
VF — Voltage Failure Bit
of the allowed range. The bit is set if either the LVIF or the
HVIF in the Interrupt Flag register is set.
Analog Integrated Circuit Device Data
Freescale Semiconductor
Reset
Read
Write
These read/write bits enable the user to select the
The high speed slew rates are used, for example, for
This read only bit is set if the LIN transmitter operates in
This read only bit is a copy of the HTIF bit in the Interrupt
This read only bit indicates that the supply voltage was out
SRS1
0
0
1
1
1 = transmitter operating in current limitation region
0 = transmitter not operating in current limitation region
1 = overtemperature condition
0 = no overtemperature condition
1 = low/high voltage condition detected
0 = no voltage failure condition detected
LINC
Register Name and Address: SYSSTAT - $0C
Bit7
Table 11. LIN Slew Rate Selection Bits
L
0
SRS0
HTIF
Figure 25. VF flag generation
HVIF
LVIF
0
1
0
1
6
0
VF
5
0
H0F
Initial Slew Rate (20kBaud)
Slow Slew Rate (10kBaud)
4
0
High Speed II (8x)
High Speed I (4x)
HVD
DF
Slew rate
3
0
VF
HSF
2
0
HBF
1
0
Bit0
0
0
H0F — H0 Failure Bit
Status and Control Register (HLSCTL)
HVDDF— HVDD Failure Bit
High-Side Status register
HSF— HS1:3 Failure Bit
side outputs is present
HBF— HB1:4 Failure Bit
bridge outputs is present.
WINDOW WATCHDOG
recover from e.g. code runaways or similar conditions.
the watchdog clear has not only to occur but to be done at a
certain time frame / window.
Normal mode
mode and is ceased in Stop and Sleep mode. On setting the
WDRE bit, the watchdog functionality is activated. Once this
This read only bit is a copy of the H0OCF bit in the H0/L0
This read only bit is a copy of the HVDDOCF bit in the
This read only bit is set if a fail condition on one of the high-
This read only bit is set if a fail condition on one of the half
The window watchdog is to supervise the device and to
The use of a window watchdog adds additional safety as
The window watchdog function is just available in Normal
1 = overcurrent detected on H0
0 = no overcurrent on H0
1 = HVDD terminal fail
0 = HVDD normal operating
1 = HS1:3 terminal fail
0 = HS1:3 normal operating
1 = HB1:4 terminal overcurrent fail
0 = HB1:4 normal operating
HS1OCF
HS2OCF
HS3OCF
HB1OCF
HB2OCF
HB3OCF
HB4OCF
Figure 26. HSF flag generation
Figure 27. HBF flag generation
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
HBF
HSF
908E621
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