xa3s1400a-4ftg256q Xilinx Corp., xa3s1400a-4ftg256q Datasheet - Page 52

• Manufacturer Part Number: xa3s1400a-4ftg256q
• Description: Xa Spartan-3a Automotive Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

Byte Peripheral Interface Configuration Timing
Table 53: Timing for BPI Configuration Mode
52
(Open-Drain)
T
T
T
T
T
T
T
T
CCLK1
CCLKn
MINIT
INITM
INITADDR
CCO
DCC
CCD
Symbol
PROG_B
LDC[2:0]
PUDC_B
CSO_B
A[25:0]
INIT_B
(Input)
(Input)
(Input)
(Input)
M[2:0]
D[7:0]
CCLK
HDC
Shaded values indicate specifications on attached parallel NOR Flash PROM.
Initial CCLK clock period
CCLK clock period after FPGA loads ConfigRate setting
Setup time on M[2:0] mode pins before the rising edge of INIT_B
Hold time on M[2:0] mode pins after the rising edge of INIT_B
Minimum period of initial A[25:0] address cycle; LDC[2:0] and HDC are asserted
and valid
Address A[25:0] outputs valid after CCLK falling edge
Setup time on D[7:0] data inputs before CCLK rising edge
Hold time on D[7:0] data inputs after CCLK rising edge
T
MINIT
<0:1:0>
PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process.
Figure 14: Waveforms for BPI Configuration
T
INITM
Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low.
Pin initially high-impedance (Hi-Z) if PUDC_B input is High.
Description
000_0000
T
CCLK1
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Mode input pins M[2:0] are sampled when INIT_B goes High. After this point,
input values do not matter until DONE goes High, at which point the mode pins
become user-I/O pins.
Byte 0
T
INITADDR
000_0001
Byte 1
T
AVQV
Data
New ConfigRate active
Minimum
T
CCLK1
Address
50
T
0
0
5
See TSMDCC in
CCO
DS681 (v1.1) February 3, 2009
Data
See
See
See
T
T
DCC
CCLKn
Address
Product Specification
Maximum
Table 45
Table 45
Table 49
–
–
5
–
Data
Table 50
DS529-3_05_121107
Address
T
cycles
Units
T
CCLK1
Data
CCD
ns
ns
ns
R