xa3s100e Xilinx Corp., xa3s100e Datasheet - Page 31

• Manufacturer Part Number: xa3s100e
• Description: Xa Spartan-3e Automotive Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

Master Serial and Slave Serial Mode Timing
Table 39: Timing for the Master Serial and Slave Serial Configuration Modes
DS635 (v1.1) January 20, 2009
Product Specification
Notes:
1.
2.
Clock-to-Output Times
T
Setup Times
T
Hold Times
T
Clock Timing
T
T
F
Symbol
CCO
DCC
CCD
CCH
CCL
CCSER
The numbers in this table are based on the operating conditions set forth in
For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.
R
The time from the falling transition on the CCLK pin to data
appearing at the DOUT pin
The time from the setup of data at the DIN pin to the active edge of
the CCLK pin
The time from the active edge of the CCLK pin to the point when
data is last held at the DIN pin
High pulse width at the CCLK input pin
Low pulse width at the CCLK input pin
Frequency of the clock signal at
the CCLK input pin
Description
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Table
6.
Master
Master
Master
Slave/
Slave
Slave
Slave
Both
Both
Both
-4 Speed Grade
11.0
Min
1.5
0
0
0
See
See
See
See
Table 37
Table 38
Table 37
Table 38
66
Max
10.0
20
-
-
(2)
Units
MHz
MHz
ns
ns
ns
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