xa3s100e Xilinx Corp., xa3s100e Datasheet - Page 21

• Manufacturer Part Number: xa3s100e
• Description: Xa Spartan-3e Automotive Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

Table 22: CLB Distributed RAM Switching Characteristics
Table 23: CLB Shift Register Switching Characteristics
DS635 (v1.1) January 20, 2009
Product Specification
Clock-to-Output Times
Setup Times
Hold Times
Clock Pulse Width
Clock-to-Output Times
Setup Times
Hold Times
Clock Pulse Width
T
T
WPH
WPH
T
Symbol
Symbol
T
T
T
AH,
T
SRLDH
SHCKO
SRLDS
T
T
T
T
REG
WS
, T
DS
AS
DH
, T
T
WH
WPL
WPL
R
Time from the active edge at the CLK input to data appearing on the shift
register output
Setup time of data at the BX or BY input before the active transition at the
CLK input of the shift register
Hold time of the BX or BY data input after the active transition at the CLK
input of the shift register
Minimum High or Low pulse width at CLK input
Time from the active edge at the CLK input to data appearing on the
distributed RAM output
Setup time of data at the BX or BY input before the active transition at the
CLK input of the distributed RAM
Setup time of the F/G address inputs before the active transition at the CLK
input of the distributed RAM
Setup time of the write enable input before the active transition at the CLK
input of the distributed RAM
Hold time of the BX, BY data inputs after the active transition at the CLK
input of the distributed RAM
Hold time of the F/G address inputs or the write enable input after the active
transition at the CLK input of the distributed RAM
Minimum High or Low pulse width at CLK input
Description
Description
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0.46
0.52
0.40
0.15
1.01
Min
0.46
0.16
1.01
Min
0
-
-
-4
-4
Max
2.35
Max
4.16
-
-
-
-
-
-
-
-
-
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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