saa7167 NXP Semiconductors, saa7167 Datasheet - Page 7

• Manufacturer Part Number: saa7167
• Description: Yuv-to-rgb Digital-to-analog Converter Dac
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 4 Pixel byte sequence of 5 : 6 : 5
For RGB 5 : 6 : 5 video inputs, the video data are just
directly bypassed to triple DACs.
The input video data can be selected to either two’s
complement (I
(DRP-bit = 1). The video input format is selected by
I
The rising edge of HREF input defines the start of active
video data. When HREF is inactive, the video output will be
blanked.
YUV-
The matrix converts YUV data, in accordance with
CCIR-601, to RGB data with approximately 1.5 LSB
deviation to the theoretical values for 8-bit resolution.
T
Three identical DACs for R, G and B video outputs are
designed with voltage-drive architecture to provide
high-speed operation of up to 50 MHz conversion data
rate. A C
de-coupling capacitor to be connected between the
internal reference voltage source and ground.
1995 Nov 03
2
UV7
UV6
UV5
UV4
UV3
UV2
UV1
UV0
YUV7
YUV6
YUV5
YUV4
YUV3
YUV2
YUV1
YUV0
RGB data
RIPLE
C-bus bits FMTC1 and FMTC0.
YUV-to-RGB Digital-to-Analog
Converter (DAC)
INPUT
TO
8-
-RGB
ref(h)
BIT
DAC
pin is provided to allow for one external
MATRIX
2
C-bus DRP-bit = 0) or binary offset
S
PIXEL BYTE SEQUENCE OF RGB
G0
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
B4
B3
B2
B1
B0
0
G0
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
B4
B3
B2
B1
B0
1
5 : 6 : 5
G0
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
B4
B3
B2
B1
B0
2
G0
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
B4
B3
B2
B1
B0
3
7
Analog mixers and keying control
The analog mixers are controlled to switch between the
outputs from the video DACs and analog RGB inputs by a
keying signal. The analog RGB inputs need to interface
with analog mixers in the way of DC-coupling, also these
RGB inputs are limited to RGB signals without a sync level
pedestal. The keying control can be enabled by setting I
bit KEN = 1. Two kinds of keying are possible to generate:
one is external key (from EXTKEY pin when
KMOD2 to KMOD0 are logic 0), and the other is the
internal pixel colour key (when KMOD2 to KMOD0 are not
logic 0) generated by comparing the input pixel data with
the internal I
by KMOD2 to KMOD0 bits, there are 4 ways to compare
the pixel data (see Table 5).
Table 5 KMOD2 to KMOD0
Since only one control register KD7 to KD0 provides the
data value for pixel data comparison, when at 2
3
bytes (lower, middle, or higher) of each pixel must be same
as KD7 to KD0 in order to make graphics colour key
active.
The polarity of EXTKEY can be selected with KINV. With
KINV = 0, EXTKEY = HIGH switches analog mixers to
select DAC outputs. Before the internal keying signal
switches the analog multiplexers, it can be further delayed
up to 7 PCLK cycles with the control bits
KDLY2 to KDLY0.
KMOD2
KMOD0
8-bit pixel input modes, it is presumed that all input
100
101
110
111
to
2
8-bit pixel
2
2
3
C-bus register value KD7 to KD0. Controlled
PIXEL TYPE
8-bit pixel
8-bit pixel
8-bit pixel
pseudo colour mode
high colour mode 1 with
pixels given at both rising
and falling edges of PCLK
high colour mode 2 with
pixels given only at rising
edges of PCLK
true colour mode
Preliminary specification
REMARK
SAA7167
8-bit or
2
C