saa7167ah NXP Semiconductors, saa7167ah Datasheet - Page 7

• Manufacturer Part Number: saa7167ah
• Description: Saa7167 Yuv-to-rgb Digital-to-analog Converter
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 4 Pixel byte sequence of 5 : 6 : 5
For RGB 5 : 6 : 5 video inputs, the video data are just
directly bypassed to triple DACs.
The input video data can be selected to either twos
complement (I
(I
by I
The rising edge of HREF input defines the start of active
video data. When HREF is inactive, the video output will be
blanked.
YUV-
The matrix converts YUV data, in accordance with
ITU-R BT.601, to RGB data with approximately 1.5 LSB
deviation to the theoretical values for 8-bit resolution.
T
Three identical DACs for R, G and B video outputs are
designed with voltage-drive architecture to provide
high-speed operation of up to 66 MHz conversion data
rate. Pin C_REF(H) is provided to allow for one external
de-coupling capacitor to be connected between the
internal reference voltage source and ground.
2004 Jun 29
UV7
UV6
UV5
UV4
UV3
UV2
UV1
UV0
YUV7
YUV6
YUV5
YUV4
YUV3
YUV2
YUV1
YUV0
RGB data
2
RIPLE
C-bus bit DRP = 1). The video input format is selected
YUV-to-RGB digital-to-analog
converter
2
C-bus bits FMTC[1:0].
INPUT
TO
8-
-RGB
BIT
DAC
MATRIX
2
C-bus bit DRP = 0) or binary offset
S
PIXEL BYTE SEQUENCE OF RGB
G0
G5
G4
G3
G2
G1
R4
R3
R2
R1
R0
B4
B3
B2
B1
B0
0
G0
G5
G4
G3
G2
G1
R4
R3
R2
R1
R0
B4
B3
B2
B1
B0
1
5 : 6 : 5
G0
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
B4
B3
B2
B1
B0
2
G0
G5
G4
G3
G2
G1
R4
R3
R2
R1
R0
B4
B3
B2
B1
B0
3
7
Analog mixers and keying control
The analog mixers are controlled to switch between the
outputs from the video DACs and analog RGB inputs by a
keying signal. The analog RGB inputs need to interface
with analog mixers in the way of DC-coupling, also these
RGB inputs are limited to RGB signals without a sync level
pedestal. The keying control can be enabled by setting
I
generate: one is external key (from EXTKEY pin when
KMOD[2:0] are all logic 0), and the other is the internal
pixel colour key (when KMOD[2:0] are not all logic 0)
generated by comparing the input pixel data with the
internal I
KMOD[2:0] bits, there are 4 ways to compare the pixel
data (see Table 5).
Table 5 KMOD[2:0]
Since only one control register KD[7:0] provides the data
value for pixel data comparison, when at 2
3
bytes (lower, middle or higher) of each pixel must be the
same as KD[7:0] in order to make graphics colour key
active.
The polarity of EXTKEY can be selected with KINV. With
KINV = 0, EXTKEY = HIGH switches analog mixers to
select DAC outputs. Before the internal keying signal
switches the analog multiplexers, it can be further delayed
up to 7 PCLK cycles with the control bits KDLY[2:0].
2
KMOD[2:0] PIXEL TYPE
C-bus bit KEN = 1. Two kinds of keying are possible to
8-bit pixel input modes, it is presumed that all input
100
101
110
111
2
C-bus register value KD[7:0]. Controlled by
8-bit pixel
2
2
3
8-bit pixel high colour mode 1 with
8-bit pixel high colour mode 2 with
8-bit pixel true colour mode
pseudo colour mode
pixels given at both rising
and falling edges of PCLK
pixels given only at rising
edges of PCLK
SAA7167AH
Product specification
REMARK
8-bit or