saa7199b NXP Semiconductors, saa7199b Datasheet - Page 12

• Manufacturer Part Number: saa7199b
• Description: Digital Video Encoder Denc Genlock-capable
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 6 Bit allocation map (I
Notes
1. DF is the default value for a typical programming example: GENLOCK mode for a VCR; non-gamma-corrected RGB
2. Read only bits.
3. Reserved.
4. Adjust as required.
1996 Sep 27
Input processing
0000 0000
0000 0001
0000 0010
0000 0011
Sync processing
0000 0100
0000 0101
0000 0110
0000 0111
Control, clock and output formatter
0000 1000
0000 1001
0000 1010
0000 1011
Encoder control
0000 1100
0000 1101
0000 1110
0000 1111
Digital Video Encoder (DENC)
GENLOCK-capable
BINARY
data (real time keying is possible). SLT will be set if there is no horizontal lock.NTSC-M standard with normal colour
bandwidth and 12.2727 MHz pixel rate. CSYN signal will be provided, arriving 8 pixel clocks earlier, to compensate
pipeline delay in the previous RAM interface. The encoded CVBS is 12 clocks earlier than the CVBS reference on
the input of the previous ADC. The CLUTs are bypassed at MPK = HIGH in real time.
INDEX
(3)
(3)
(3)
HEX
0A
0B
0F
0C
0D
0E
00
01
02
03
04
05
06
07
08
09
(3)
(3)
(3)
VTBY
TRER7
TREG7
TREB7
SYSEL1 SYSEL0 SCEN
0
IDEL7
0
DD
0
0
0
CHPS7
FSCO7
0
0
D7
2
C-bus access in Table 17)
FMT2
TRER6
TREG6
TREB6
0
IDEL6
0
KEYE
BAME
0
0
CHPS6
FSCO6
0
0
D6
FMT1
TRER5
TREG5
TREB5
GDC5
IDEL5
PSO5
SRC
MPKC1
0
0
CHPS5
FSCO5
0
0
D5
FMT0
TRER4
TREG4
TREB4
VTRC
GDC4
IDEL4
PSO4
CPR
MPKC0
0
0
CHPS4
FSCO4
CLCK
0
12
D4
DATA BYTE
(2)
SCBW
TRER3
TREG3
TREB3
NINT
GDC3
IDEL3
PSO3
COKI
IEPI
0
0
CHPS3
FSCO3
STD3
0
D3
CCIR
TRER2
TREG2
TREB2
HPLL
GDC2
IDEL2
PSO2
IM
RTSC
0
0
CHPS2
FSCO2
STD2
0
D2
MOD1
TRER1
TREG1
TREB1
HLCK
GDC1
IDEL1
PSO1
GPSW
RTIN
0
0
CHPS1
FSCO1
STD1
0
D1
(2)
Product specification
MOD0
TRER0
TREG0
TREB0
OEF
GDC0
IDEL0
PSO0
SRSN
RTCE
0
0
CHPS0
FSCO0
STD0
0
SAA7199B
D0
(2)
5C
XX
XX
XX
10
21
52
32
64
02
00
00
XX
00
0C
DF
(4)
(1)