saa7120 NXP Semiconductors, saa7120 Datasheet - Page 19

• Manufacturer Part Number: saa7120
• Description: Digital Video Encoder Condenc
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 25 Logic levels and function of SRCV1
Table 26 Subaddress 6C and 6D
Table 27 Subaddress 6D
Table 28 Subaddress 6E
Table 29 Logic levels and function of PHRES
1997 Jan 06
HTRIG
VTRIG
SBLBN
PHRES
FLC
DATA BYTE
DATA BYTE
DATA BYTE
Digital Video Encoder (ConDENC)
PHRES1
SRCV11
0
0
1
1
0
0
1
1
DATA BYTE
DATA BYTE
sets the horizontal trigger phase related to signal on RCV1 or RCV2 input
sets the vertical trigger phase related to signal on RCV1 input
PHRES0
SRCV10
values above 1715 (FISE = 1) or [1727 (FISE = 0)] are not allowed
increasing HTRIG decreases delays of all internally generated timing signals
reference mark: analog output horizontal sync (leading slope) coincides with active edge of RCV used
for triggering at HTRIG = 398H [398H]
increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines
variation range of VTRIG = 0 to 31 (1FH)
LEVEL
LOGIC
0
1
0
1
0
1
0
1
0
1
vertical blanking is defined by programming of FAL and LAL; default after reset
vertical blanking is forced in accordance with “CCIR 624” (50 Hz) or RS170A (60 Hz)
selects the phase reset mode of the colour subcarrier generator; see Table 29
field length control; see Table 30
no reset or reset via RTCI from SAA7111 if bit RTCE = 1; default after reset
reset every two lines
reset every eight fields
reset every four fields
not applicable
AS OUTPUT
FSEQ
VS
FS
not applicable
AS INPUT
FSEQ
VS
FS
19
DESCRIPTION
DESCRIPTION
vertical sync each field; default after reset
frame sync (odd/even)
field sequence, vertical sync every fourth field
(PAL = 0) or eighth field (PAL = 1)
DESCRIPTION
DESCRIPTION
FUNCTION
SAA7120; SAA7121
Preliminary specification