saa7121h-v2 NXP Semiconductors, saa7121h-v2 Datasheet - Page 26
saa7121h-v2
Manufacturer Part Number
saa7121h-v2
Description
Digital Video Encoder
Manufacturer
NXP Semiconductors
Datasheet
1.SAA7121H-V2.pdf
(36 pages)
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Philips Semiconductors
2002 Oct 11
handbook, full pagewidth
handbook, full pagewidth
Digital video encoder
The data demultiplexing phase is coupled to the internal horizontal phase.
The phase of the RCV2 signal is programmed to 262 for 50 Hz and to 234 for 60 Hz in this example in output mode (RCV2S).
LLC clock output
LLC clock input
input data
output data
LLC
MP(n)
RCV2
t SU; DAT
valid
valid
t HD; DAT
t HD; DAT
t HD; DAT
C B (0)
t HIGH
t HIGH
Fig.7 Clock data timing.
Fig.8 Functional timing.
Y(0)
t d
not valid
not valid
26
T LLC
T LLC
t f
t f
C R (0)
SAA7120H; SAA7121H
Y(1)
t r
t r
valid
valid
Product specification
MBE742
C B (2)
MGB699
2.6 V
1.5 V
0.6 V
2.4 V
1.5 V
0.8 V
2.0 V
0.8 V
2.4 V
0.6 V
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