saa7118 NXP Semiconductors, saa7118 Datasheet - Page 131

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saa7118

Manufacturer Part Number
saa7118
Description
Multistandard Video Decoder With Adaptive Comb Filter And Component Video Input
Manufacturer
NXP Semiconductors
Datasheet

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Philips Semiconductors
Table 102: I port FIFO flag control and arbitration; global set 86h[3:0]
[1]
Table 103: I port I/O enable, output clock and gated clock phase control; global set 87h[7:4]
[1]
[2]
Table 104: I port I/O enable, output clock and gated clock phase control; global set 87h[1:0]
9397 750 15219
Product data sheet
I port FIFO flag control and arbitration
FAE FIFO flag almost empty level
FAF FIFO flag almost full level
Output clock and gated clock phase control
ICLK default output phase
ICLK phase shifted by
ICKS0 = 0 (subaddress 80h)
ICLK phase shifted by approximately 3 ns
ICLK phase shifted by
3 ns
IDQ = gated clock default output phase
IDQ = gated clock phase shifted by
gated clock output
IDQ = gated clock phase shifted by approximately 3 ns
IDQ = gated clock phase shifted by
3 ns
I port I/O enable
I port output is disabled by software
I port output is enabled by software
I port output is enabled by pin ITRI at logic 0
I port output is enabled by pin ITRI at logic 1
< 16 Dwords
< 8 Dwords
< 4 Dwords
0 Dwords
32 Dwords
X = don’t care.
X = don’t care.
IPCK3 and IPCK2 only affects the gated clock (subaddress 80h, bit ICKS2 = 1).
16 Dwords
24 Dwords
28 Dwords
alternatively to setting ‘01’
alternatively to setting ‘01’
1
1
2
2
clock cycle
clock cycle + approximately
1
1
2
2
clock cycle
clock cycle + approximately
recommended for ICKS1 = 1 and
Rev. 06 — 22 December 2005
recommended for
Multistandard video decoder with adaptive comb filter
Control bits D3 to D0
FFL1
X
X
X
X
0
0
1
1
Control bits D7 to D4
IPCK3
X
X
X
X
0
0
1
1
Control bits D1 and D0
IPE1
0
0
1
1
[1]
[2]
FFL0
X
X
X
X
0
1
0
1
IPCK2
X
X
X
X
0
1
0
1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
[2]
[1]
IPE0
0
1
0
1
FEL1
0
0
1
1
X
X
X
X
IPCK1
0
0
1
1
X
X
X
X
SAA7118
FEL0
0
1
0
1
X
X
X
X
IPCK0
0
1
0
1
X
X
X
X
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