dsp56002fc80 Freescale Semiconductor, Inc, dsp56002fc80 Datasheet - Page 36

• Manufacturer Part Number: dsp56002fc80
• Description: 24-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

Specifications
RESET, Stop, Mode Select, and Interrupt Timing
2-10
Notes:
Num
28 Delay from Level Sensitive IRQA Assertion to Fetch of First
A0-A15,
CKOUT
RESET
DS, PS
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing (All Frequencies) (Continued)
A0–A15
RESET
Interrupt Instruction (when exiting ‘Stop’)
X/Y
1.
2.
3.
•
•
•
• after power-on reset, and
• when recovering from Stop mode.
During this stabilization period, T
programs.
Circuit stabilization delay is required during reset when using an external clock in two cases:
• after power-on reset, and
• when recovering from Stop mode.
When using fast interrupts and IRQA and IRQB are defined as level-sensitive, then timings 19 through
22 apply to prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-
triggered mode is recommended when using fast interrupt. Long interrupts are recommended when
using Level-sensitive mode.
A clock stabilization delay is required when using the on-chip crystal oscillator in two cases:
varies, a delay of 75,000 T
Internal Crystal Oscillator Clock, OMR bit 6 = 0
Stable External Clock, OMR bit 6 = 1
Stable External Clock, PCTL bit 17= 1
9
12
Characteristics
Figure 2-5 Synchronous Reset Timing
C
is typically allowed to assure that the oscillator is stable before executing
Figure 2-4 Reset Timing
DSP56002/D, Rev. 3
C
, T
H,
10
and T
1
L
13
will not be constant. Since this stabilization period
65548T
20T
13T
Min
C
C
C
11
First Fetch
Max
V
MOTOROLA
—
—
—
IHR
AA0356
AA0357
Unit
ns
ns
ns