dsp56002fc80 Freescale Semiconductor, Inc, dsp56002fc80 Datasheet - Page 25

• Manufacturer Part Number: dsp56002fc80
• Description: 24-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
Signal Name
DSO
DR
Output
Signal
Input
Table 1-13 On-Chip Emulation (OnCE) Signals (Continued)
Type
during
Pulled
Reset
Input
State
high
Debug Serial Output—Data contained in one of the OnCE
controller registers is provided through the DSO output signal,
as specified by the last command received from the external
command controller. Data is always shifted out the OnCE serial
port Most Significant Bit (MSB) first. Data is clocked out of the
OnCE serial port on the rising edge of DSCK.
The DSO signal also provides acknowledge pulses to the
external command controller. When the chip enters the Debug
mode, the DSO signal will be pulsed low to indicate
(acknowledge) that the OnCE is waiting for commands. After
the OnCE receives a read command, the DSO signal will be
pulsed low to indicate that the requested data is available and
the OnCE serial port is ready to receive clocks in order to deliver
the data. After the OnCE receives a write command, the DSO
signal will be pulsed low to indicate that the OnCE serial port is
ready to receive the data to be written; after the data is written,
another acknowledge pulse will be provided.
Note:
Debug Request—The debug request input (DR) allows the user
to enter the Debug mode of operation from the external
command controller. When DR is asserted, it causes the DSP to
finish the current instruction being executed, save the instruction
pipeline information, enter the Debug mode, and wait for
commands to be entered from the DSI line. While in Debug
mode, the DR signal lets the user reset the OnCE controller by
asserting it and deasserting it after receiving acknowledge. It
may be necessary to reset the OnCE controller in cases where
synchronization between the OnCE controller and external
circuitry is lost. DR must be deasserted after the OnCE responds
with an acknowledge on the DSO signal and before sending the
first OnCE command. Asserting DR will cause the chip to exit
the Stop or Wait state. Having DR asserted during the
deassertion of RESET will cause the DSP to enter Debug mode.
Note:
DSP56002/D, Rev. 3
Connect an external pull-up resistor to this signal.
Connect an external pull-up resistor to this signal.
Signal Description
On-Chip Emulation Port
Signal/Pin Descriptions
1-19