dsp56001 Freescale Semiconductor, Inc, dsp56001 Datasheet - Page 29

• Manufacturer Part Number: dsp56001
• Description: Available In An 88 Pin Ceramic Through-hole Package.
• Manufacturer: Freescale Semiconductor, Inc

DSP56001
1. For internal clock, External Clock Cycle is defined by Icyc and SSI control register.
Num
101a TXC Falling Edge to Data Out High
100
101
102
103
104
105
106
93
94
95
96
97
98
99
Flags Input Setup Before RXC Falling
Edge
Flags Input Hold Time After RXC
Falling Edge
TXC Rising Edge to FST Out (bl) High
TXC Rising Edge to FST Out (bl) Low
TXC Rising Edge to FST Out (wl) High
TXC Rising Edge to FST Out (wl) Low
TXC Rising Edge to Data Out Enable
from High Impedance
TXC Rising Edge to Data Out Valid
TXC Rising Edge to Data Out High
Impedance (periodically sampled, and
not 100% tested)
Impedance for Gated Clock Mode Only
FST Input (bl) Setup Time Before TXC
Falling Edge
FST Input (wl) to Data Out Enable from
High Impedance
FST Input (wl) Setup Time Before TXC
Falling Edge
FST Input Hold Time After TXC Falling
Edge
Flag Output Valid After TXC Rising
Edge
AC Electrical Characteristics - SSI Timing (Continued)
Note:
Note:
1. For internal clock, External Clock Cycle is defined by Icyc and SSI control register.
Characteristics
DSP56001 Electrical Characteristics
i ck a
x ck
x ck
x ck
x ck
x ck
x ck
x ck
i ck a
i ck a
i ck a
i ck a
i ck a
i ck a
i ck a
i ck a
i ck a
i ck a
i ck a
i ck a
x ck
x ck
x ck
x ck
g ck
x ck
x ck
cyc+tch
Min
30
50
35
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
35
—
20
55
35
—
—
5
5
20.5 MHz
Max
70
30
65
35
65
35
65
35
65
40
65
40
70
40
60
70
40
—
—
—
—
—
—
—
—
—
—
—
cyc+tch
Min
23
39
27
12
27
15
42
27
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
4
27 MHz
Max
54
23
50
27
50
27
50
27
50
31
50
31
54
31
46
54
31
—
—
—
—
—
—
—
—
—
—
—
cyc+tch
Min
19
31
22
10
23
13
34
22
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
4
33 MHz
Max
MOTOROLA
—
—
—
—
43
19
40
22
40
22
40
22
40
25
40
25
43
25
—
—
37
—
—
—
—
43
25
—
Unit
nss
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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