dsp56001 Freescale Semiconductor, Inc, dsp56001 Datasheet - Page 18

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dsp56001

Manufacturer Part Number
dsp56001
Description
Available In An 88 Pin Ceramic Through-hole Package.
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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18
Num
32a
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
Host Synchronous Delay (see Note 1)
HEN/HACK Assertion Width
a.CVR, ICR, ISR Read (see Note 4)
b.Read
c.Write
HEN/HACK Deassertion Width
Minimum Cycle Time Between Two
HEN Assertion for Consecutive CVR,
ICR, and ISR Reads
Host Data Input Setup Time Before
HEN/HACK Deassertion
Host Data Input Hold Time After HEN/
HACK Deassertion
HEN/HACK Assertion to Output Data
Active from High Impedance
HEN/HACK Assertion to Output Data
Valid (periodically sampled, and not
100% tested)
HEN/HACK Deassertion to Output
Data High Impedance
Output Data Hold Time After HEN/
HACK Deassertion
HR/W Low Setup Time Before HEN
Assertion
HR/W Low Hold Time After HEN
Deassertion
HR/W High Setup Time to HEN
Assertion
HR/W High Hold Time After HEN/
HACK Deassertion
HA0-HA2 Setup Time Before HEN
Assertion
HA0-HA2 Hold Time After HEN
Deassertion
DMA HACK Assertion to HREQ
Deassertion
(Vcc = 5.0 Vdc + 10%, T
(Vcc = 5.0 Vdc + 5%, T
(see Host Figures 1 through 6)
cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles
tHSDL = Host Synchronization Delay Time
Active low lines should be “pulled up” in a manner consistent with the AC and DC specifications
Characteristics
(see Note 2 and 5)
AC Electrical Characteristics - Host I/O Timing
(see Note 2)
DSP56001 Electrical Characteristics
(see Note 2)
(see Note 3)
J
J
= -40 to +105° C, CL = 50 pf + 1 TTL Load at 33 MHz)
= -40 to +105° C, CL = 50 pf + 1 TTL Load at 20.5 MHz and 27 MHz)
2
cyc+60
*
cyc+60
Min
50
25
25
tcl
5
5
0
5
0
5
0
5
0
5
5
20.5 MHz
cyc+tcl
Max
50
35
60
2
cyc+46
*
cyc+46
Min
39
19
19
tcl
4
4
0
4
0
4
0
4
0
4
4
27 MHz
cyc+tcl
Max
39
27
46
2
cyc+37
*
cyc+37
Min
31
16
16
tcl
4
4
0
4
0
4
0
4
0
4
4
33 MHz
cyc+tcl
Max
31
22
49
DSP56001
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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