dsp56853 Freescale Semiconductor, Inc, dsp56853 Datasheet - Page 44

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dsp56853

Manufacturer Part Number
dsp56853
Description
16-bit Digital Signal Controllers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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44
Delay from SCK high to SC2 (wl) high - Master
Delay from SC0 high to SC1 (bl) high - Master
Delay from SC0 high to SC1 (wl) high - Master
Delay from SCK high to SC2 (bl) low - Master
Delay from SCK high to SC2 (wl) low - Master
Delay from SC0 high to SC1 (bl) low - Master
Delay from SC0 high to SC1 (wl) low - Master
SCK high to STD enable from high impedance - Master
SCK high to STD valid - Master
SCK high to STD not valid - Master
SCK high to STD high impedance - Master
SRD Setup time before SC0 low - Master
SRD Hold time after SC0 low - Master
SRD Setup time before SCK low - Master
SRD Hold time after SCK low - Master
Operating Conditions: V
1. Master mode is internally generated clocks and frame syncs
2. Max clock frequency is IP_clk/4 = 60MHz / 4 = 15MHz for an 120MHz part.
3. All the timings for the ESSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)
4. 50 percent duty cycle
5. bl = bit length; wl = word length
and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync
have been inverted, all the timings remain valid by inverting the clock signal SCK/SC0 and/or the frame sync SC2/SC1 in
the tables and in the figures.
Table 4-12 ESSI Master Mode
Synchronous Operation (in addition to standard internal clock parameters)
SS
= V
SSIO
Parameter
= V
SSA
= 0 V, V
DD
56853 Technical Data, Rev. 6
= 1.62-1.98V, V
5
5
5
5
5
5
5
1
Switching Characteristics (Continued)
DDIO
= V
DDA
= 3.0–3.6V, T
Symbol
t
t
t
t
t
t
RFSWHM
t
TFSWHM
RFSWLM
RFSBHM
TFSWLM
t
RFSBLM
TFSBLM
t
TXNVM
t
t
TXHIM
t
TXEM
TXVM
t
t
t
TSM
THM
HM
SM
A
= –40° to +120°C, C
Min
-1.0
-1.0
-1.0
-1.0
-1.0
-1.0
-1.0
-0.1
-0.1
-0.1
-4
4
4
4
4
Typ
Freescale Semiconductor
L
≤ 50pF, f
Max
1.0
1.0
1.0
1.0
1.0
1.0
1.0
2
2
0
op
= 120MHz
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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