adsp-2196m Analog Devices, Inc., adsp-2196m Datasheet - Page 30

• Manufacturer Part Number: adsp-2196m
• Description: Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

ADSP-2196
External Port Read Cycle Timing
Table 12
discussion on
Table 12. External Port Read Cycle Timing
1
2
3
4
30
t
These are preliminary timing parameters that are based on worst-case operating conditions.
The pad loads for these timing parameters are 20 pF.
EMI clock is the external port clock that is generated from the EMI clock ratio. This signal is not available on an external pin, but (roughly) corresponds
to HCLK (at similar clock ratios).
Parameter
Switching Characteristics
t
t
t
t
t
t
t
t
Timing Requirements
t
t
t
t
t
t
t
HCLK
CRA
CSRS
ARS
AKS
CRD
RSCS
RW
RSA
AKW
CDA
RDA
ADA
SDA
SD
HRD
is the peripheral clock period.
and
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
Figure 15
on page
Description
EMI
Chip select asserted to RD asserted delay
Address valid to RD setup and delay
ACK asserted to EMI clock high delay
EMI clock low to RD de-asserted delay
RD de-asserted to chip select de-asserted setup
RD strobe pulsewidth
RD de-asserted to address invalid setup
ACK strobe pulsewidth
RD to data enable access delay
RD asserted to data access setup
Address valid to data access setup
Chip select asserted to data access setup
Data valid to RD de-asserted setup
RD de-asserted to data invalid hold
4
clock low to RD asserted delay
28.
describe external port read operations. For additional information on the ACK signal, see the
1, 2, 3
For current information contact Analog Devices at 800/262-5643
Min
4.3
4.9
6.0
2.5
4.8
t
4.5
10.0
0.0
1.8
0.0
HCLK
–0.5
September 2001
Max
2.8
6.5
7.0
2.7
7.0
6.6
t
t
t
HCLK
HCLK
HCLK
–5.5
–0.2
–0.6
REV. PrA
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns