adsp-21371 Analog Devices, Inc., adsp-21371 Datasheet - Page 38

• Manufacturer Part Number: adsp-21371
• Description: Sharc Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21371
S/PDIF Receiver
The following section describes timing as it relates to the
S/PDIF receiver.
Internal Digital PLL Mode
In the internal digital phase-locked loop mode the internal PLL
(digital PLL) generates the 512
Table 36. S/PDIF Receiver Internal Digital PLL Mode Timing
1
Parameter
Switching Characteristics
t
t
t
t
t
SCLK frequency is 64 × FS where FS = the frequency of LRCLK.
DFSI
HOFSI
DDTI
HDTI
SCLKIW
1
LRCLK Delay After SCLK
LRCLK Hold After SCLK
Transmit Data Delay After SCLK
Transmit Data Hold After SCLK
Transmit SCLK Width
× FS clock.
(DATA CHANNEL A/B)
DAI_P20-1
Figure 28. S/PDIF Receiver Internal Digital PLL Mode Timing
DAI_P20-1
DAI_P20-1
(SCLK)
(FS)
DRIVE EDGE
Rev. 0 | Page 38 of 48 | June 2007
t
t
HOFSI
HDTI
t
DFSI
t
SCLKIW
t
DDTI
Min
–2
–2
38.5
SAMPLE EDGE
Max
5
5
Unit
ns
ns
ns
ns
ns