xcr3320 Xilinx Corp., xcr3320 Datasheet - Page 18

• Manufacturer Part Number: xcr3320
• Description: Xcr3320 320 Macrocell Sram Cpld
• Manufacturer: Xilinx Corp.

In applications in which a serial EEPROM stores multiple
configuration programs, the subsequent configuration pro-
gram(s) are stored in EEPROM locations that follow the
last address for the previous configuration program. The
user must ensure that the serial EEPROMs address pointer
is not reset, causing the first device configuration to be
reloaded.
Contention on the XCR3320’s din pin must be avoided.
During configuration, din receives configuration data. After
configuration, it is a user I/O.
DS033 (v1.3) October 9, 2000
Figure 20:
A[19:0]
DOUT
D[7:0]
CCLK
Master Parallel Configuration Mode Timing Diagram
R
This product has been discontinued. Please see
PROM PROGRAMMER
BYTE N
jed2mcs
t
CH
DESIGN COMPILATION AND FIT
D0
t
CL
t
D
D1
www.xilinx.com
1-800-255-7778
D2
jed
D3
BYTE N
Master Parallel Mode
The master parallel configuration mode is generally used to
interface to industry-standard byte-wide memory such as
256K and larger EEPROMs.
face for master parallel mode. The XCR3320 outputs a
20-bit address on A[19:0] to memory and reads one byte of
configuration data every eighth cclk. The parallel bytes are
internally serialized starting with the least significant bit,
D0. The starting memory address is 00000 Hex and the
XCR3320 increments the address for each byte loaded.
The starting address is output when the device enters the
configuration state. The XCR3320 latches the data byte on
the second rising edge of cclk. This next data byte is
latched in the XCR3320 seven cclk cycles later.
SLAVE SERIAL CONFIGURA TION
t
D4
S
BYTE N + 1
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XCR3320: 320 Macrocell SRAM CPLD
D5
download
D6
D7
SP00676
t
H
D0
BYTE N + 1
Figure 19
D1
Figure 19: Master
D2
provides the inter-
D3
SP00585
for details.
18