epm3064a Altera Corporation, epm3064a Datasheet - Page 29
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epm3064a
Manufacturer Part Number
epm3064a
Description
Programmable Logic Device Family
Manufacturer
Altera Corporation
Datasheet
1.EPM3064A.pdf
(46 pages)
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Altera Corporation
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Symbol
IN
IO
SEXP
PEXP
LAD
LAC
IOE
OD1
OD2
OD3
ZX1
ZX2
ZX3
XZ
SU
H
RD
COMB
IC
EN
GLOB
PRE
CLR
Table 17. EPM3032A Internal Timing Parameters (Part 1 of 2)
Input pad and buffer delay
I/O input pad and buffer
delay
Shared expander delay
Parallel expander delay
Logic array delay
Logic control array delay
Internal output enable delay
Output buffer and pad
delay, slow slew rate = off
V
Output buffer and pad
delay, slow slew rate = off
V
Output buffer and pad
delay, slow slew rate = on
V
Output buffer enable delay,
slow slew rate = off
V
Output buffer enable delay,
slow slew rate = off
V
Output buffer enable delay,
slow slew rate = on
V
Output buffer disable delay C1 = 5 pF
Register setup time
Register hold time
Register delay
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
= 3.3 V
= 2.5 V
= 2.5 V or 3.3 V
= 3.3 V
= 2.5 V
= 2.5 V or 3.3 V
Parameter
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
C1 = 35 pF
Conditions
MAX 3000A Programmable Logic Device Family Data Sheet
Min
1.3
0.6
–4
Max
0.7
0.7
1.9
0.5
1.5
0.6
0.0
0.8
1.3
5.8
4.0
4.5
9.0
4.0
0.7
0.6
1.2
0.6
0.8
1.2
1.2
Note (1)
Speed Grade
Min
2.0
1.0
–7
Max
1.2
1.2
3.1
0.8
2.5
1.0
0.0
1.3
1.8
6.3
4.0
4.5
9.0
4.0
1.2
1.0
2.0
1.0
1.3
1.9
1.9
Min
2.8
1.3
–10
Max
10.0
1.5
1.0
3.3
5.0
1.3
2.5
1.9
2.6
1.5
4.0
1.2
0.0
1.8
2.3
6.8
5.0
5.5
1.5
1.2
2.6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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