x79002 Intersil Corporation, x79002 Datasheet - Page 13

• Manufacturer Part Number: x79002
• Description: Nv Dac With Selectable Output Range And Memory
• Manufacturer: Intersil Corporation

Table 1. Control Registers
IDENTIFICATION AND MEMORY ADDRESS BYTES
The first byte sent to the X79000, following a falling edge
at the CS pin, is called the “Identification Byte”. The most
significant bit (ID7) is the function selector bit. The next
six bits (ID6-ID1) are the Device Address bits (AS5-AS0).
To communicate to the X79000, the value of bits AS[5:0]
must correspond to the logic levels at pins A5, A4, A3,
A2, A1, and A0 respectively. If one or more of the
address pins doesn’t exist in a particular device, then the
corresponding device address bits must be set to “0”.
The LSB (ID0) is the R/W bit. This bit defines the
operation to be performed on the device being
addressed. When the R/W bit is “1”, then a Read
operation is selected. A “0” selects a write operation.
If the value of the Device Address bits doesn’t match the
logic levels at the Address pins, then the Read or Write
operation is aborted.
Non-Volatile
Non-volatile
Non-volatile
Volatile or
Volatile or
Address
Volatile
Byte
3Ch
3Fh
38h
39h
Bytes at addresses 3Ah, 3Bh, 3Dh, and 3Eh are reserved.
Full Scale Configuration
000: External VH reference
001: 605mV
010: 1.21V
011: 1.815V
100: 2.42V
101: 3.025V
110, 111: Reserved
NVDAC
DAC11
DAC3
VH2
MSB
7
13
Reserved
DAC10
DAC2
VH1
6
Reserved Reserved
DAC9
DAC1
VH0
5
X79000, X79001, X79002
Zero Level Configuration
000: External VL reference
001: 151mV
010: 605mV
011: 1.21V
100: 1.815V
101: 2.42V
110, 111: Reserved
DAC8
DAC0
VL2
4
Reserved
Reserved
DAC7
VL1
3
The byte sent to the X79000, immediately following the
Identification byte, is called the Memory Address Byte.
The value of this byte is the location of the first byte to
be written to, or read from the X79000. Valid values for
this byte are from 00h to 3Fh. If the value of the
“Memory Address byte” is invalid, the Read or Write
operation is aborted.
Slave Address
ID7
1
Reserved
Reserved
ID6-ID1
DAC6
VL0
Bit(s)
ID7
ID0
AS5
2
ID6
AS4
ID5
Reserved
Counter Configuration
(for Up/Down Operation)
00: 12 bits
01: 10 bits
10: 8 bits
11: Reserved
Reserved
Count8
DAC5
1
AS3
ID4
Function Selector bit
Device Address
Read or Write Operation Select
Address
Device
Reserved
Reserved
Count10
AS2
ID3
DAC4
LSB
0
Description
ID2
AS1
MSBs of DAC
Register
LSBs of DAC
Register
Configuration
Register
Non-Volatile
Write Enable
Register
Name
AS0
ID1
Read or
Write
R/W
ID0
March 17, 2005
FN8147.0