adv7441a Analog Devices, Inc., adv7441a Datasheet
adv7441a
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adv7441a Summary of contents
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... To facilitate professional applications, where HDCP processing and decryption is not required, a derivative part of the ADV7441A is available. This allows users who are not HDCP adopters to purchase the ADV7441A. See the Ordering Guide for details. ...
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... Modes Section ................................................................................. 14 Changes to Table 8 .......................................................................... 18 Added Table 9 .................................................................................. 18 Added Table 10 ............................................................................... 19 Added Table 11 ............................................................................... 20 Added AD9388A/ADV7441A Evaluation System Section ....... 25 Updated Outline Dimensions ....................................................... 26 Changes to Ordering Guide .......................................................... 26 10/07—Revision Sp0: Initial Version Standard Definition Processor Pixel Data Output Modes .... 14 Component Processor Pixel Data Output Modes .................. 14 Composite and S-Video Processing ...
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... FUNCTIONAL BLOCK DIAGRAM FORMATTER OUTPUT CONTROL OVERLAY MUX RECOVERY EQUALIZER Figure 1. Rev Page ADV7441A 06914-001 BLANK FAST CONVERSION 4:4:4 TO 4:2:2 PROCESSOR PACKET EEPROM XOR HDCP ENGINE HDCP DECODE HDMI DDCB_SCL ALIGNMENT CONTROLLER DDCB_SDA DATA EDID/REPEATER DDCA_SDA DDCA_SCL MUX MUX EQUALIZER ...
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... ADV7441A SPECIFICATIONS ELECTRICAL CHARACTERISTICS AVDD = 1. 1.89 V, DVDD = 1. 1.98 V, DVDDIO = 2. 3.63 V, PVDD = 1. 1.89 V, TVDD = 3.135 V to 3.465 V, CVDD = 1. 1.89 V. Operating temperature range is −40°C to +85°C, unless otherwise noted. Table 1. 1 Parameter 2 STATIC PERFORMANCE Resolution (Each ADC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS ...
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... Graphics RGB sampling @ 108 MHz SCART RGB fast blank sampling @ 54 MHz YPrPb 1080p sampling @ 148.5 MHz HDMI RGB sampling @ 165 MHz HDMI RGB sampling @ 225 MHz I PWRDN t PWRUP = 48 kHz, and MCLKOUT = 256 f S Rev Page ADV7441A Min Typ Max ...
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... ADV7441A VIDEO SPECIFICATIONS AVDD = 1. 1.89 V, DVDD = 1. 1.98 V, DVDDIO = 2. 3.63 V, PVDD = 1. 1.89 V, TVDD = 3.135 V to 3.465 V, CVDD = 1. 1.89 V. Operating temperature range is −40°C to +85°C, unless otherwise noted. Table Parameter NONLINEAR SPECIFICATIONS Differential Phase Differential Gain Luma Nonlinearity NOISE SPECIFICATIONS SNR Unweighted ...
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... S-Video input (C signal) Component input (Y signal) Component input (Pr signal) Component input (Pb signal) PC RGB input ( signals) SDP only SDP only SDP only SDP only to T MIN Rev Page ADV7441A Typ Max 0 0.88 CML + 0.5 CML − 0.5 1 CML – 0.122 CML – 0.167 CML– ...
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... ADV7441A TIMING CHARACTERISTICS AVDD = 1. 1.89 V, DVDD = 1. 1.98 V, DVDDIO = 2. 3.63 V, PVDD = 1. 1.89 V, TVDD = 3.135 V to 3.465 V, CVDD = 1. 1.89 V. Operating temperature range is −40°C to +85°C, unless otherwise noted. Table Parameter SYSTEM CLOCK AND CRYSTAL Crystal Nominal Frequency Crystal Frequency Stability Horizontal Sync Input Frequency ...
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... Figure 3. Pixel Port and Control SDR Output Timing (SDP Core Figure 4. Pixel Port and Control SDR Output Timing (CP Core MSB MSB – MSB MSB – MSB 2 Figure Timing Rev Page LSB t 20 ADV7441A ...
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... Table 6. Package Type 144-Lead LQFP (ST-144) 1 Junction-to-package surface thermal resistance. PACKAGE THERMAL PERFORMANCE To reduce power consumption during ADV7441A operation, turn off unused ADCs four-layer PCB that includes a solid ground plane, the value of θ is 25.3°C/W. However, due to variations within the JA PCB metal and, therefore, variations in PCB heat conductivity, the value of θ ...
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... HDMI Comparator, TMDS PLL, and Equalizer Supply Voltage (1.8 V). P Terminator Supply Voltage (3.3 V). I Fast Blank. Fast switch overlay between CVBS and RGB analog signals. I Test Pins. Do not connect. O Test Pin. Do not connect. Rev Page ADV7441A TEST5 108 TEST4 107 106 DDCA_SDA DDCA_SCL 105 104 ...
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... Line-Locked Output Clock for Pixel Data. Range is 13.5 MHz to 170 MHz. O This pin should be connected to the 28.63636 MHz crystal or left connect if an external 3.3 V 28.63636 MHz clock oscillator source is used to clock the ADV7441A. In crystal mode, the crystal must be a fundamental crystal. I Input Pin for the 28.63636 MHz Crystal. This pin can be overdriven by an external 3 ...
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... Audio Serial Clock Output. O Audio Master Clock Output. I External Clamp Signal Input for External Clock and Clamp Mode. This is an optional mode of operation for the ADV7441A. I Clock Input for External Clock and Clamp Mode. This is an optional mode of operation for the ADV7441A. I Sets internal termination resistance. Connect this pin to TGND using a 500 Ω ...
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... ADV7441A. More details are available in the Theory of Operation section. ANALOG FRONT END The analog front end of the ADV7441A provides four high quality 10-bit ADCs to enable 10-bit video decoding, a multiplexer with 12 analog input channels to enable multisource connection without the requirement of an external multiplexer, and four current and voltage clamp control loops to ensure that dc offsets are removed from the video signal ...
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... Data enable (DE) output signal supplied for direct connection to the HDMI/DVI transmitter IC. GENERAL FEATURES The ADV7441A features HS, VS, and FIELD output signals with programmable position, polarity, and width; and programmable interrupt request output pins, INT1 and INT2. The part also offers low power consumption: 1.8 V digital core, 1 ...
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... The ADV7441A SDP section has a Macrovision 7.1 detection circuit that allows it to detect Type I, Type II, and Type III protection levels. The decoder is fully robust to all Macrovision signal inputs ...
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... VGA up to UXGA at 60 Hz, and many other standards. The CP section of the ADV7441A contains an AGC block. This block is followed by a digital clamp circuit that ensures that the video signal is clamped to the correct blanking level. Automatic adjustments within the CP include gain (contrast) and offset (brightness) ...
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... ADV7441A PIXEL OUTPUT FORMATTING Note that unused pins of the pixel output port are driven with a low voltage. Table 8. Standard Definition Pixel Port Modes (P19 to P0) Processor Mode/Format SDP Mode 1 Video output 8-bit 4:2:2 SDP Mode 2 Video output 10-bit 4:2:2 SDP Mode 3 Video output 16-bit 4:2:2 ...
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... YCrCb[11:4] – CHA[7:0] (default data is Y[7:0]) – CHA[9:0] (default data is Y[9:0]) CHA[9:2] (default data is Y[9:2]) – Y[11:2] Y[11:4] – Y[11:4] – – – – – CHA[9:0] (default data is G[9:0] or Y[9:0]) Rev Page ADV7441A – – – – – – – – – – ...
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... ADV7441A 1 Processor Mode/Format 19 CP Mode 17 Video output 3, 4 30-bit 4:4:4 CP Mode 18 Video output 30-bit 4:4 Mode 19 Video output 30-bit 4:2 processor uses digitizer or HDMI as input. 2 Maximum pixel clock rate of 54 MHz. 3 Maximum pixel clock rate of 170 MHz (analog digitizer). 4 Maximum pixel clock rate of 165 MHz (HDMI). ...
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... Maximum pixel clock rate of 165 MHz (HDMI). Output of Data Port Pins P[29:20 CHB[7:0] (for example, R[7:0] or Cr[7:0]) CHB[7:0] (for example, R[7:0] or Cr[7:0]) CHA[7:0] (for example, G[7:0] or Y[7:0]) CHC[9:0] (for example, B[9:0] or Cb[9:0]) CHB[9:0] (for example, R[9:0] or Cr[9:0]) CHB[9:0] (for example, R[9:0] or Cr[9:0]) CHA[9:0] (for example, G[9:0] or Y[9:0]) Rev Page ADV7441A – – – 20 – – – ...
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... HDMI Map 0x68 Repeater KSV Map 0x64 EDID Map 0x6C USER MAP SA: 0x40 SCL SDA PROGRAMMABLE 2 C-compatible) interface. The ADV7441A has eight maps, each with a unique Default Address with ALSB = High Programmable Address 0x42 Not programmable 0x46 Programmable 0x62 Programmable 0x4A Programmable ...
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... TYPICAL CONNECTION DIAGRAM Figure 8. Typical Connection Diagram Rev Page ADV7441A ...
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... ADV7441A RECOMMENDED EXTERNAL LOOP FILTER COMPONENTS Note that the external loop filter components for the ELPF and AUDIO_ELPF pins should be placed as close as possible to the respective pins. The recommended component values are specified in Figure 9 and Figure 10. ELPF 70 10nF 1.69kΩ PVDD = 1.8V 82nF Figure 9 ...
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... The front end of the platform consists of an EVAL- AD9388AFEZ_x or EVAL-ADV7441AFEZ_x board. This board feeds the digital outputs from the decoder to the FPGA on the motherboard. The EVAL-AD9388AFEZ_x or EVAL- ADV7441AFEZ_x board comes with one of the pin-compatible decoders shown in Table 13. On-Board Decoder ADV7441ABSTZ-170 ADV7441ABSTZ-5P ...
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... Professional version for nonHDCP encrypted applications. Purchaser is not required HDCP adopter. 5 Front-end board for new evaluation platform; fitted with ADV7441ABSTZ-170 decoder. See the AD9388A/ADV7441A Evaluation Platform section for details on evaluation platform. 6 Front-end board for new evaluation platform; fitted with ADV7441ABSTZ-5P decoder. See the AD9388A/ADV7441A Evaluation Platform section for details on evaluation platform ...
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... NOTES Rev Page ADV7441A ...
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... ADV7441A NOTES ©2007–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06914-0-7/08(B) Rev Page ...