adv7310 Analog Devices, Inc., adv7310 Datasheet - Page 37

• Manufacturer Part Number: adv7310
• Description: Multiformat 216 Mhz Video Encoder With Six Nsv 12-bit Dacs
• Manufacturer: Analog Devices, Inc.

Reset Sequence
A reset is activated with a high-to-low transition on the RESET
pin [Pin 33] according to the timing specifications. The ADV7310/
ADV7311 will revert to the default output configuration.
Figure 32 illustrates the RESET sequence timing.
SD VCR FF/RW Sync
[Subaddress 42h, Bit 5]
In DVD record applications where the encoder is used with a
decoder, the VCR FF/RW sync control bit can be used for non-
standard input video, i.e., in fast forward or rewind modes.
REV. A
DIGITAL TIMING
PIXEL DATA
NOTES
1
2
3
4
5
RTC
i.e., VCR OR CABLE
F
SEQUENCE BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE
RESET ADV7310/ADV7311 DDS
SELECTED BY REGISTER ADDRESS 0x01 BIT 7
PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS
OF THE ADV7310/ADV7311.
SC
RESET
A, B, C
PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7310/ADV7311 F
VALID
DACs
COMPOSITE
XXXXXX
XXXXXX
H/L TRANSITION
VIDEO
COUNT START
TIME SLOT 01
128
1
LOW
ADV7183A
DECODER
VIDEO
13
LCC1
SUBCARRIER
PHASE
14 BITS
Figure 32. RTC Timing and Connections
P19–P10
Figure 33. RESET Timing Sequence
RESERVED
GLL
14
0
4 BITS
DIGITAL TIMING SIGNALS SUPPRESSED
21
19
–37–
CLKIN_A
RTC_SCR_TR
Y9-Y0/S9–S0
OFF
SAMPLE
ADV7310/
ADV7311
F
In fast forward mode, the sync information at the start of a new
field in the incoming video usually occurs before the correct num-
ber of lines/fields are reached; in rewind mode, this sync signal
usually occurs after the total number of lines/fields are reached.
Conventionally this means that the output video will have cor-
rupted field signals, one generated by the incoming video and
one generated when the internal lines/field counters reach the
end of a field.
When the VCR FF/RW sync control is enabled [Subaddress 42h
Bit 5] the lines/field counters are updated according to the
incoming VSYNC signal and the analog output matches the
incoming VSYNC signal.
This control is available in all slave timing modes except Slave
Mode 0.
VALID
SC
PLL INCREMENT
5
SC
INVALID
SAMPLE
DDS REGISTER IS F
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
2
LOCKED
CLOCK
8/LINE
SC
PLL INCREMENTS BITS 21:0
SEQUENCE
BIT
0
ADV7310/ADV7311
3
RESERVED
6768
5 BITS
RESET
RESERVED
BIT
4
TIMING ACTIVE
VALID VIDEO