adv7310 Analog Devices, Inc., adv7310 Datasheet
adv7310
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adv7310 Summary of contents
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... It includes six high speed NSV video D/A converters with TTL compatible inputs. The ADV7310/ADV7311 has separate 8-/10-/16-/20-bit input ports that accept data in high definition and/or standard definition video format. For all standards, external horizontal, vertical, ...
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... HD High Definition Video, i.e., Progressive Scan or HDTV. PS Progressive Scan Video, conforming to SMPTE 293M, ITU-R BT.1358, BTAT-1004EDTV2, or BTA1362. *ADV7310 Only Controlled Edge Rates for Sync, Active Video Individual Y and PrPb Output Delay Gamma Correction Digital Noise Reduction (DNR) Multiple Chroma and Luma Filters Luma-SSAF™ ...
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... Programming the RGB Matrix . . . . . . . . . . . . . . . . . . . . . 45 SD Luma and Color Control . . . . . . . . . . . . . . . . . . . . . . 45 SD Hue Adjust Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 SD Brightness Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 SD Brightness Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Double Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 REV. A ADV7310/ADV7311 PROGRAMMABLE DAC GAIN CONTROL . . . . . . . . . . 47 Gamma Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 HD SHARPNESS FILTER CONTROL AND ADAPTIVE FILTER CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 HD Sharpness Filter Mode . . . . . . . . . . . . . . . . . . . . . . . 49 HD Adaptive Filter Mode . . . . . . . . . . . . . . . . . . . . . . . . 49 HD Sharpness Filter and Adaptive Filter Application Examples ...
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... ADV7310/ADV7311–SPECIFICATIONS V = 2.375–3 1.235 V, R DD_IO REF SET Parameter 1 STATIC PERFORMANCE Resolution Integral Nonlinearity 2 Differential Nonlinearity , +ve 2 Differential Nonlinearity , –ve DIGITAL OUTPUTS Output Low Voltage Output High Voltage Three-State Leakage Current Three-State Output Capacitance DIGITAL AND CONTROL INPUTS ...
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... C), unless otherwise noted.) MIN MAX Min Typ 12.5 5.8 65 13.75 0.2 0.20 0.84 –0.2 0 96.7 –1.0 0.2 84 75.3 0.25 0.2 63.5 77.7 –5– ADV7310/ADV7311 = 2.375 V–3 1.235 V, R DD_IO REF Max Unit Test Conditions MHz MHz dB Luma ramp unweighted dB Flat field full bandwidth MHz MHz o % ± % Referenced to 40 IRE ± o ± % ± ± % ...
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... ADV7310/ADV7311 TIMING SPECIFICATIONS R = 300 . All specifications LOAD MIN MAX Parameter 1 MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth SCLOCK Low Pulsewidth Hold Time (Start Condition Setup Time (Start Condition Data Setup Time SDATA, SCLOCK Rise Time, t ...
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... Figure 2. HD Only 4:4:4 Input Mode [Input Mode 010]; PS Only 4:4:4 Input Mode [Input Mode 001] REV Cb0 Cr0 Cb2 Cr2 Cb0 Cb1 Cb2 Cb3 Cr1 Cr 2 Cr3 –7– ADV7310/ADV7311 Y4 Y5 Cb4 Cr4 Cb4 Cb5 Cr5 t 14 ...
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... ADV7310/ADV7311 CLKIN_A P_HSYNC, CONTROL P_VSYNC, INPUTS P_BLANK Y9–Y0 C9–C0 S9–S0 CONTROL OUTPUTS t = CLOCK HIGH TIME CLOCK LOW TIME DATA SETUP TIME DATA HOLD TIME 12 Figure 3. HD RGB 4:4:4 Input Mode [Input Mode 010] CLKIN_B* P_HSYNC, CONTROL P_VSYNC, INPUTS P_BLANK Y9– ...
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... Interleaved at 27 MHz EAV/SAV Input Mode [Input Mode 100 3FF NOTE: Y0, Cb0 SEQUENCE AS PER SUBADDRESS 0 10-Bit Interleaved at 54 MHz EAV/SAV Input Mode [Input Mode 111] –9– ADV7310/ADV7311 Crxxx Yxxx Cb0 Y0 Cr0 Cb0 Y0 Cr0 Y1 01 BIT-1 ...
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... ADV7310/ADV7311 CLKIN_B P_HSYNC, CONTROL P_VSYNC, INPUTS P_BLANK Y9–Y0 Y0 C9–C0 Cb0 CLKIN_A t S_HSYNC, CONTROL S_VSYNC, INPUTS S_BLANK S9–S0 Cb0 Figure 8. HD 4:2:2 and SD (10-Bit) Simultaneous Input Mode [Input Mode 101: SD Oversampled] [Input Mode 110: HD Oversampled] CLKIN_B P_HSYNC, CONTROL P_VSYNC, INPUTS P_BLANK Y9–Y0 Y0 C9– ...
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... Figure 11. 10-/8-Bit SD Only Pixel Input Mode [Input Mode 000] REV Crxxx Y0 Cr0 Cr0 Cb1 Cr0 Cb2 Cr2 Cb4 –11– ADV7310/ADV7311 PS INPUT Yxxx Y2 IN SLAVE MODE Cr4 IN MASTER/SLAVE MODE SD INPUT ...
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... ADV7310/ADV7311 CLKIN_A t 9 S_HSYNC, CONTROL S_VSYNC, INPUTS S_BLANK S9–S0/Y9–Y0* C9–C0 CONTROL OUTPUTS *SELECTED BY ADDRESS 0x01 BIT 7 Figure 12. 20-/16-Bit SD Only Pixel Input Mode [Input Mode 000] P_HSYNC P_VSYNC P_BLANK Y9–Y0 C9– CLKCYCLES FOR 525p CLKCYCLES FOR 626p CLKCYCLES FOR 1080i @ 30Hz, 25Hz ...
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... SCLK REV 10-Bit Interleaved Input Timing Diagram Figure 15. SD Timing Input for Timing Mode Figure 16. MPU Port Timing Diagram –13– ADV7310/ADV7311 PAL = 24 CLK CYCLES NTSC = 32 CLK CYCLES ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7310/ADV7311 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... S0. For 8-bit data input, LSB is set up on S2. RESET I This input resets the on-chip timing generator and sets the ADV7310/ADV7311 into default register setting. RESET is an active low signal. A 3040 Ω resistor must be connected from this pin to AGND and is used to control the amplitudes ...
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... In write mode, the data for the invalid byte will not be loaded A1 X into any subaddress register, a no-acknowledge will be issued ADDRESS by the ADV7310/ADV7311, and the part will return to the CONTROL idle condition. SET UP BY ALSB Before writing to the subcarrier frequency registers require- ...
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... P = STOP BIT REGISTER ACCESSES The MPU can write to or read from all of the registers of the ADV7310/ADV7311 except the subaddress registers, which are write only registers. The subaddress register determines which register the next read or write operation accesses. All communi- cations with the part through the bus start with an access to the subaddress register ...
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... ADV7310/ADV7311 SR7– SR0 Register Bit Description 00h Power Mode Sleep Mode. With this Register control enabled, the current consumption is reduced to µA level. All DACs and the internal 2 PLL cct are disabled registers can be read from and written to in Sleep Mode ...
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... ADV7310/ADV7311 Reset Bit 0 Register Setting Values 0 Zero must be written to 20h these bits Disabled Enabled 0x11h, Bit 2 must also be enabled Disable Programmable RGB matrix Enable Programmable RGB matrix No Sync Sync on all RGB outputs ...
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... ADV7310/ADV7311 SR7– SR0 Register Bit Description 10h HD Mode HD Output Standard Register 1 HD Input Control Signals HD 625p HD 720p HD BLANK Polarity HD Macrovision for 525p/625p 11h HD Mode HD Pixel Data Valid Register 2 HD Test Pattern Enable HD Test Pattern Hatch/Field HD VBI Open HD Undershoot Limiter HD Sharpness Filter ...
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... ADV7310/ADV7311 Bit 2 Bit 1 Bit 0 Register Setting 0 Cb after falling edge of HSYNC 1 Cr after falling edge of HSYNC 0 0 must be written to this bit 0 8-bit input 1 10-bit input Disabled Enabled 0 must be written to this ...
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... ADV7310/ADV7311 SR7– SR0 Register Bit Description 16h HD Y Level* 17h HD Cr Level* 18h HD Cb Level* 19h Reserved 1Ah Reserved 1Bh Reserved 1Ch Reserved 1Dh Reserved 1Eh Reserved 1Fh Reserved 20h HD Sharpness Filter HD Sharpness Filter Gain Value A Gain HD Sharpness Filter Gain Value B ...
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... ADV7310/ADV7311 Register Reset Bit 0 Setting Values 0 Gain 00h 1 Gain …… 1 Gain Gain A = –8 .. …… 1 Gain A = –1 Gain Gain ……. Gain Gain B = – ...
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... ADV7310/ADV7311 SR7– SR0 Register Bit Description 3Eh Reserved 3Fh Reserved 40h SD Mode Register 0 SD Standard SD Luma Filter SD Chroma Filter 41h Reserved 42h SD Mode Register 1 SD PrPb SSAF SD DAC Output 1 SD DAC Output 2 SD Pedestal SD Square Pixel SD VCR FF/RW Sync SD Pixel Data Valid ...
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... ADV7310/ADV7311 Reset Bit 0 Register Setting Values 0 Disabled 00h VSYNC = 2.5 lines [PAL] 1 VSYNC = 3 lines [NTSC] Genlock disabled Subcarrier Reset Timing Reset RTC enabled 720 pixels 710 [NTSC]/702[PAL] Chroma enabled Chroma disabled ...
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... ADV7310/ADV7311 SR7– SR0 Register Bit Description 4Ah SD Timing SD Slave/Master Mode Register 0 SD Timing Mode SD BLANK Input SD Luma Delay SD Min. Luma Value SD Timing Reset SD HSYNC Width 4Bh SD Timing Register 1 SD HSYNC to VSYNC delay SD HSYNC to VSYNC Rising Edge Delay [Mode 1 Only] VSYNC Width [Mode 2 Only] ...
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... ADV7310/ADV7311 Bit 1 Bit 0 Register Setting 17 16 CGMS data bits C19–C16 Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled 9 8 CGMS data bits C13–C8 or WSS data bits C13–C8 CGMS data bits C15– ...
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... ADV7310/ADV7311 SR7– SR0 Register Bit Description 65h SD DNR 2 DNR Input Select DNR Mode DNR Block Offset 66h SD Gamma A SD Gamma Curve A Data Points 67h SD Gamma A SD Gamma Curve A Data Points 68h SD Gamma A SD Gamma Curve A Data Points 69h SD Gamma A SD Gamma Curve A Data Points ...
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... Macrovision MV Control Bits 8Dh Macrovision MV Control Bits 8Eh Macrovision MV Control Bits 8Fh Macrovision MV Control Bits 90h Macrovision MV Control Bits 91h Macrovision MV Control Bit NOTE Macrovision registers only on the ADV7310. REV. A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit ...
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... Address 0x7C, Bit 1 (Global 10-Bit Enable) Address 0x13, Bit 2 (HD 10-Bit Enable) Address 0x48, Bit 4 (SD 10-Bit Enable) Note that the ADV7310 defaults to simultaneous standard definition and progressive scan on power-up. Address[01h] : Input Mode = 011 Standard Definition Only Address[01h] : Input Mode = 000 The 8-/10-bit multiplexed input data is input on Pins S9– ...
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... Figure 27c. Input Sequence in PS Bit Interleaved Mode (EAV/SAV) MPEG2 DECODER 27MHz OR 54MHz YCrCb INTERLACED YCrCb TO PROGRESSIVE Figure 28. 1 10-Bit MHz or 54 MHz Table I provides an overview of all possible input configurations. –31– Cb0 Y0 Cr0 Y1 Y0 Cb0 Y1 Cr0 XY Cb0 Y0 Cr0 Y1 ADV7310/ ADV7311 CLKIN_A 10 Y[9:0] P_VSYNC 3 P_HSYNC P_BLANK ...
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... ADV7310/ADV7311 Input Format Total Bits ITU-R BT.656 Only 8 [27 MHz clock] 10 [27 MHz clock] 8 [54 MHz clock] 10 [54 MHz clock HDTV Only RGB 24 30 ITU-R BT.656 and ITU-R BT.656 and ITU-R BT.656 and PS or HDTV ...
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... N/A N N/A 0 N/A 1 N/A HD/PS Color Swap 15h, Bit 3 DAC A DAC B CVBS Luma 0 1 CVBS Luma CVBS Luma 0 1 CVBS Luma –33– ADV7310/ADV7311 DAC B DAC C DAC D DAC E Luma Chroma CVBS Luma Luma Chroma CVBS Luma Luma Chroma CVBS ...
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... For any input data that does not conform to the standards select- able in input mode, Subaddress 10h, asynchronous timing mode can be used to interface to the ADV7310/ADV7311. Timing control signals for HSYNC, VSYNC, and BLANK have to be programmed by the user. Macrovision and programmable oversampling rates are not available in async timing mode ...
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... The minimum time the pin has to be held high is one clock cycle; otherwise, this reset signal might not be recognized. This timing reset applies to the HD timing counters only. –35– ADV7310/ADV7311 Reference in Figure ...
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... Field 1, being lined up correctly with the internal counters. The field count register at Address 7Bh can be used to iden- tify the number of the active field RTC mode, the ADV7310/ADV7311 can be used to lock to an external video source. The real-time control mode allows the ADV7310/ADV7311 to automatically alter the subcarrier frequency to compensate for line length variations ...
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... RTC TIME SLOT 01 NOTES 1 i.e., VCR OR CABLE 2 F PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7310/ADV7311 F SC PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7310/ADV7311. 3 SEQUENCE BIT PAL LINE NORMAL LINE INVERTED NTSC CHANGE ...
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... ADV7310/ADV7311 Vertical Blanking Interval The ADV7310/ADV7311 accept input data that contains VBI data [CGMS, WSS, VITS, and so on and HD modes. For SMPTE 293M [525p] standards, VBI data can be inserted on Lines each frame Lines for the ITU-R BT.1358 [625p] standard. ...
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... FILTER SECTION Table VI shows an overview of the programmable filters available on the ADV7310/ADV7311. Table VI. Selectable Filters Filter Subaddress SD Luma LPF NTSC 40h SD Luma LPF PAL 40h SD Luma Notch NTSC 40h SD Luma Notch PAL 40h SD Luma SSAF 40h SD Luma CIF 40h SD Luma QCIF 40h SD Chroma 0 ...
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... C [Subaddress 62h]. The variation of fre- quency responses can be seen in the figures on the following pages. In addition to the chroma filters listed in Table VII, the ADV7310/ADV7311 contains an SSAF filter specifically designed for and applicable to the color difference component outputs, U and V. This filter has a cutoff frequency of about 2.7 MHz and – ...
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... Typical Performance Characteristics–ADV7310/ADV7311 PROG SCAN Pr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4 0 –10 –20 –30 –40 –50 –60 –70 – 100 120 FREQUENCY (MHz) TPC 1. PS—UV 8 × Oversampling Filter (Linear) PROG SCAN Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4 0 –10 –20 – ...
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... ADV7310/ADV7311 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) TPC 7. Luma NTSC Low-Pass Filter 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) TPC 8. Luma PAL Low-Pass Filter 0 –10 –20 –30 –40 –50 –60 – ...
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... TPC 17. Luma QCIF Low-Pass Filter 0 –10 –20 –30 –40 –50 –60 – TPC 18. Chroma 3.0 MHz Low-Pass Filter –43– ADV7310/ADV7311 FREQUENCY (MHz) TPC 16. Luma CIF Low-Pass Filter FREQUENCY (MHz FREQUENCY (MHz) ...
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... ADV7310/ADV7311 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) TPC 19. Chroma 2.0 MHz Low-Pass Filter 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) TPC 20. Chroma 1.3 MHz Low-Pass Filter 0 –10 –20 –30 –40 –50 –60 – ...
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... B' − When the programmable RGB matrix is not enabled, the − ADV7310/ADV7311 automatically scales YCrCb inputs all standards supported by this part. SD Luma and Color Control [Subaddress 5Ch, 5Dh, 5Eh, 5Fh Scale Scale, and SD Cb Scale are three 10-bit wide control registers to scale the Y, U, and V output levels ...
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... These eight bits represent the value required to vary the hue of the video data, i.e., the variance in phase of the subcarrier during active video with respect to the phase of the subcarrier during the color burst. The ADV7310/ADV7311 provides a range 22.5 increments of 0.17578125 ...
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... ADV7310/ADV7311 Table XI. DAC Current (mA) % Gain 4.658 7.5000% 4.653 7.3820% 4.648 7.3640% ... ... ...
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... ADV7310/ADV7311 Gamma Correction [Subaddress 24h–37h for HD, Subaddress 66h–79h for SD] Gamma correction is available for SD and HD video. For each standard, there are twenty 8-bit wide registers. They are used to program the gamma correction curves A and B. HD gamma curve A is programmed at Addresses 24h to 2Dh, HD gamma curve B at 2Eh to 7h ...
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... HD SHARPNESS FILTER CONTROL AND ADAPTIVE FILTER CONTROL [Subaddress 20h, 38h–3Dh] There are three filter modes available on the ADV7310/ADV7311: sharpness filter mode and two adaptive filter modes. HD Sharpness Filter Mode To enhance or attenuate the Y signal in the frequency ranges shown in the figures below, the following register settings must be used: HD sharpness filter must be enabled and HD adaptive filter enable must be set to disabled ...
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... ADV7310/ADV7311 HD Sharpness Filter and Adaptive Filter Application Examples HD Sharpness Filter Application The HD sharpness filter can be used to enhance or attenuate the Y video output signal. The following register settings were used to achieve the results shown in the figures below. Input data was generated by an external signal source. ...
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... Bit 7]. @: 446mV : 332ns @: 12.8ms Address 00h 01h 02h 10h 11h 15h 20h 38h 39h 3Ah 3Bh 3Ch 3Dh –51– ADV7310/ADV7311 : 674mV @: 446mV : 332ns @: 12.8ms Table XV. Register Setting FCh 38h 20h 00h 85h 80h 00h ACh 9Ah 88h 28h 3Fh ...
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... ADV7310/ADV7311 SD Digital Noise Reduction [Subaddress 63h, 64h, 65h] DNR is applied to the Y data only. A filter block selects the high frequency, low amplitude components of the incoming signal [DNR input select]. The absolute value of the filter output is compared to a programmable threshold value ['DNR threshold control] ...
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... Consider the coring gain posi- tions fixed. The block offset shifts the data in steps of one pixel such that the border coring gain factors can be applied at the same position regardless of variations in input timing of the data PIXEL BLOCK –53– ADV7310/ADV7311 FILTER D FILTER C FILTER B FILTER A 0 ...
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... SAV/EAV Step Edge Control The ADV7310/ADV7311 has the capability of controlling fast rising and falling signals at the start and end of active video to minimize ringing. An algorithm monitors SAV and EAV and governs when the edges are too fast. The result will be reduced ringing at the start and end of active video for fast transitions ...
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... AD8061. More information on line driver buffering circuits is given in the relevant op amps’ data sheets. An optional analog reconstruction low-pass filter (LPF) may be required as an anti-imaging filter if the ADV7310/ADV7311 is connected to a device that requires this filtering. The filter specifications vary with the application. ...
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... OUTPUT 3 470nH 220nH 75 1 300 33pF 82pF 4 Figure 58. Example of Output Filter for HDTV, 2 × Oversampling Table XVII. Possible Output Rates From the ADV7310/ADV7311 Input Mode PLL Address 01h, Bit 6–4 Address 00h, Bit 1 SD Only Off On PS Only Off On HDTV Only ...
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... To complement the excellent noise performance of the ADV7310/ADV7311 imperative that great care be given to the PC board layout. The layout should be optimized for lowest noise on the ADV7310/ ADV7311 power and ground lines. This can be achieved by shielding the digital inputs and providing good decoupling. ...
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... DAC F 37 300 V 100 SCLK 22 100 SDA 21 ALSB SET2 3040 R 47 SET1 AGND DGND 3040 64 40 11, 57 Figure 61. ADV7310/ADV7311 Circuit Layout –58– DD_IO 1.1k RECOMMENDED EXTERNAL 100nF AD1580 FOR OPTIMUM PERFORMANCE V DD_IO DD_IO BUS V DD_IO ...
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... Bits C/W05 and C/W06 control whether or not CGMS data is output on odd and even fields. CGMS data can be transmitted only when the ADV7310/ADV7311 is configured in NTSC mode. The CGMS data is 20 bits long, and the func- tion of each of these bits is as shown in the following table. The CGMS data is preceded by a reference pulse of the same ampli- tude and duration as a CGMS bit ...
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... ADV7310/ADV7311 +700mV 70% 10% 0mV –300mV 5 +100 IRE +70 IRE 0 IRE –40 IRE 11.2 s Figure 63. Standard Definition CGMS Waveform Diagram +700mV REF 70% 10% 0mV –300mV 4T 3.128 s 90ns +700mV REF 70% 10% 0mV –300mV 4T 4.15 s 60ns REF BIT1 BIT2 .BIT20 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 Figure 62 ...
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... APPENDIX 2—SD WIDE SCREEN SIGNALING [Subaddress 59h, 5Ah, 5Bh] The ADV7310/ADV7311 support wide screen signaling (WSS) conforming to the standard. WSS data is transmitted on Line 23. WSS data can be transmitted only when the device is configured in PAL mode. The WSS data is 14 bits long, and the function of each of these bits is shown in Table XIX ...
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... Scan Line 284. The data for this operation is stored in the SD closed captioning registers [Address 51h–52h]. All clock run-in signals and timing to support closed captioning on Lines 21 and 284 are generated automatically by the ADV7310/ 50 IRE 40 IRE REFERENCE COLOR BURST FREQUENCY = F ADV7311 ...
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... APPENDIX 4—TEST PATTERNS The ADV7310/ADV7311 can generate SD and HD test patterns CH2 200mV M 10 30.6000 s Figure 68. NTSC Color Bars T 2 CH2 200mV M 10 30.6000 s Figure 69. PAL Color Bars T 2 CH2 100mV M 10 1.82380ms Figure 70. NTSC Black Bar [–21 mV, 0 mV, 3.5 mV, 7 mV, 10.5 mV, 14 mV, 18 mV, 23 mV] REV ...
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... ADV7310/ADV7311 T 2 CH2 200mV M 4 1.82872ms Figure 74. 525p Field Pattern T 2 CH2 200mV M 4 1.84176ms Figure 75. 625p Field Pattern T 2 CH2 EVEN Figure 76. 525p Black Bar [–35 mV, 0 mV, 7 mV, 14 mV, 21 mV, 28 mV CH2 EVEN Figure 77. 625p Black Bar [–35 mV, 0 mV, 7 mV, 14 mV, 21 mV, 28 mV, 35 mV] – ...
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... For 625p black bar pattern output on DAC D, the same settings 40h are used as above except that subaddress = 02h and register 40h setting = 24h; and subaddress = 10h and register setting = 50h. 08h –65– ADV7310/ADV7311 Register Subaddress Setting 00h 10h 01h 10h ...
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... Mode 0 (CCIR-656)—Slave Option (Timing Register 0 TR0 = The ADV7310/ADV7311 is controlled by the SAV (start active video) and EAV (end active video) time codes in the pixel data. All timing information is transmitted using a 4-byte synchroniza- tion pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace ...
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... Mode 0 (CCIR-656)—Master Option (Timing Register 0 TR0 = The ADV7310/ADV7311 generates H, V, and F signals required for the SAV (start active video) and EAV (end active video) time codes in the CCIR656 standard. The H bit is output on the S_HSYNC, the V bit is output on S_BLANK, and the F bit is output on S_VSYNC ...
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... V Mode 1—Slave Option (Timing Register 0 TR0 = this mode, the ADV7310/ADV7311 accept horizontal sync and odd/even field signals. A transition of the field input when HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7310/ADV7311 automatically blank all normally blank lines as per CCIR-624 ...
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... Mode 1—Master Option (Timing Register 0 TR0 = this mode, the ADV7310/ADV7311 can generate horizontal sync and odd/even field signals. A transition of the field input when HSYNC is low indicates a new frame, i.e., vertical retrace. The blank signal is optional. When the BLANK input is disabled, the ADV7310/ADV7311 automatically blank all normally blank lines as per CCIR-624 ...
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... ADV7310/ADV7311 Mode 2— Slave Option (Timing Register 0 TR0 = this mode, the ADV7310/ADV7311 accepts horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field ...
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... Mode 2—Master Option (Timing Register 0 TR0 = this mode, the ADV7310/ADV7311 can generate horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field ...
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... ADV7310/ADV7311 Mode 3—Master/Slave Option (Timing Register 0 TR0 = this mode, the ADV7310/ADV7311 accept or generate horizon- tal sync and odd/even field signals. A transition of the field input when HSYNC is high indicates a new frame, i.e., vertical retrace. ...
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... P_VSYNC P_HSYNC REV. A VERTICAL BLANKING INTERVAL VERTICAL BLANKING INTERVAL 563 564 565 566 567 568 569 Figure 91. 1080i HSYNC and VSYNC Input Timing –73– ADV7310/ADV7311 DISPLAY 560 DISPLAY 570 583 584 585 1123 ...
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... ADV7310/ADV7311 APPENDIX 7—VIDEO OUTPUT LEVELS HD YPrPb Output Levels EIA-770.2, STANDARD FOR Y INPUT CODE 940 64 EIA-770.2, STANDARD FOR Pr/Pb 960 512 64 Figure 92. EIA 770.2 Standard Output Signals (525p/625p) EIA-770.1, STANDARD FOR Y INPUT CODE 940 64 EIA-770.1, STANDARD FOR Pr/Pb 960 512 64 Figure 93. EIA 770.1 Standard Output Signals ...
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... Figure 98. SD RGB Output Levels—RGB Sync Disabled 300mV 0mV 550mV 300mV 0mV 550mV 300mV 0mV Figure 99. SD RGB Output Levels—RGB Sync Enabled –75– ADV7310/ADV7311 700mV 550mV 700mV 550mV 700mV 550mV 700mV 550mV 550mV 700mV 550mV 700mV ...
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... ADV7310/ADV7311 YUV Output Levels 280mV 220mV 160mV 60mV Figure 100. U Levels—NTSC 280mV 220mV 160mV 60mV Figure 101. U Levels—PAL 200mV 1260mV 1000mV 140mV Figure 102. U Levels—NTSC 332mV 110mV 332mV 110mV 2150mV 900mV –76– 2150mV 200mV 1260mV 1000mV 900mV 140mV Figure 103. U Levels— ...
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... REV. A 100 –50 L76 MICROSECONDS PRECISION MODE OFF SYNCHRONOUS Figure 106. NTSC Color Bars 75 –50 F1 L76 MICROSECONDS PRECISION MODE OFF SYNCHRONOUS Figure 107. NTSC Chroma –77– ADV7310/ADV7311 SYNC = A FRAMES SELECTED SYNC = B FRAMES SELECTED 1 2 ...
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... ADV7310/ADV7311 VOLTS IRE:FLT 0.6 0.4 0.2 0 –0.2 10 NOISE REDUCTION: 15.05dB APL = 44.3% 525 LINE NTSC NO FILTERING SLOW CLAMP TO 0.00 AT 6.72 s VOLTS 0.6 0.4 0.2 0 –0.2 0 NOISE REDUCTION: 0.00dB APL = 39.1% 625 LINE NTSC NO FILTERING SLOW CLAMP TO 0. L238 MICROSECONDS PRECISION MODE OFF SYNCHRONOUS Figure 108. NTSC Luma ...
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... MICROSECONDS NO BUNCH SIGNAL PRECISION MODE OFF SYNCHRONOUS Figure 110. PAL Chroma L575 MICROSECONDS NO BUNCH SIGNAL PRECISION MODE OFF SYNCHRONOUS Figure 111. PAL Luma –79– ADV7310/ADV7311 50 60 SOUND-IN-SYNC OFF FRAMES SELECTED SOUND-IN-SYNC OFF FRAMES SELECTED 1 ...
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... ADV7310/ADV7311 APPENDIX 8—VIDEO STANDARDS SMPTE 274M ANALOG WAVEFORM 4T EAV CODE INPUT PIXELS CLOCK SAMPLE NUMBER 2112 2116 2156 FVH* = FVH AND PARITY BITS SAV/EAV: LINE 1–562 SAV/EAV: LINE 563–1125 SAV/EAV: LINE 1–20; 561–583; 1124–1125 SAV/EAV: LINE 21– ...
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... Figure 116. SMPTE 296M (720p) VERTICAL BLANKING INTERVAL VERTICAL BLANKING INTERVAL 563 564 565 566 567 568 569 Figure 117. SMPTE 274M (1080i) –81– ADV7310/ADV7311 ACTIVE VIDEO ACTIVE VIDEO DISPLAY 8 ...
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... ADV7310/ADV7311 10 1. 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90 CCW OUTLINE DIMENSIONS 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64) Dimensions shown in millimeters 0.75 1.60 0.60 MAX 0. SEATING PIN 1 PLANE 0.20 0.09 VIEW 0.08 MAX COPLANARITY 0.50 BSC COMPLIANT TO JEDEC STANDARDS MS-026BCD –82– 12.00 BSC 10.00 TOP VIEW (PINS DOWN) ...
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... Revision History Location 8/03—Data Sheet changed from REV REV. A. Addition to Standards Directly Supported Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to Figure 13 notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Change to Table Updated Figure Updated Figures 59 and Change to Figure 104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Deletion of line from notes in Figure 112 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 REV. A ADV7310/ADV7311 –83– Page ...
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–84– ...