adv7342 Analog Devices, Inc., adv7342 Datasheet - Page 49

• Manufacturer Part Number: adv7342
• Description: Multiformat Video Encoder Six, 11-bit, 297 Mhz Dacs
• Manufacturer: Analog Devices, Inc.

ED/HD TIMING RESET
Subaddress 0x34, Bit 0
An ED/HD timing reset is achieved by toggling the ED/HD
timing reset control bit (Subaddress 0x34, Bit 0) from 0 to 1.
In this state, the horizontal and vertical counters remain reset.
When this bit is set back to 0, the internal counters resume
counting. This timing reset applies to the ED/HD timing
counters only.
SD SUBCARRIER FREQUENCY LOCK, SUBCARRIER
PHASE RESET, AND TIMING RESET
Subaddress 0x84, Bits[2:1]
Together with the SFL/MISO pin and SD Mode Register 4
(Subaddress 0x84, Bits[2:1]), the ADV7342/ADV7343 can be used
in timing reset mode, subcarrier phase reset mode, or SFL mode.
Timing Reset (TR) Mode
In this mode (Subaddress 0x84, Bits[2:1] = 10), a timing reset is
achieved in a low-to-high transition on the SFL/MISO pin (Pin 48).
In this state, the horizontal and vertical counters remain reset.
Upon releasing this pin (set to low), the internal counters resume
counting, starting with Field 1, and the subcarrier phase is reset.
The minimum time the pin must be held high is one clock
cycle; otherwise, this reset signal might not be recognized. This
timing reset applies to the SD timing counters only.
DISPLAY
307
NO TIMING RESET APPLIED
TIMING RESET APPLIED
NO F
F
SC
307
307
307
RESET APPLIED
SC
RESET APPLIED
DISPLAY
Figure 61. SD Subcarrier Phase Reset Timing Diagram (Subaddress 0x84, Bits [2:1] = 01)
DISPLAY
DISPLAY
Figure 60. SD Timing Reset Timing Diagram (Subaddress 0x84, Bits [2:1] = 10)
310
310
310
1
START OF FIELD 1
2
3
313
313
313
4
START OF FIELD 4 OR 8
START OF FIELD 4 OR 8
START OF FIELD 4 OR 8
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5
6
F
7
SC
Subcarrier Phase Reset (SCR) Mode
In this mode (Subaddress 0x84, Bits[2:1] = 01), a low-to-high
transition on the SFL/MISO pin (Pin 48) resets the subcarrier
phase to 0 on the field following the subcarrier phase reset. This
reset signal must be held high for a minimum of one clock cycle.
Because the field counter is not reset, it is recommended that
the reset signal be applied in Field 7 (PAL) or Field 3 (NTSC).
The reset of the phase then occurs on the next field, that is,
Field 1, lined up correctly with the internal counters. The field
count register at Subaddress 0xBB can be used to identify the
number of the active field.
Subcarrier Frequency Lock (SFL) Mode
In this mode (Subaddress 0x84, Bits[2:1] = 11), the ADV7342
/ADV7343 can be used to lock to an external video source. The
SFL mode allows the ADV7342/ADV7343 to automatically alter
the subcarrier frequency to compensate for line length
variations. When the part is connected to a device such as an
ADV7403 video decoder (see Figure 62) that outputs a digital
data stream in the SFL format, the part automatically changes to
the compensated subcarrier frequency on a line-by-line basis.
This digital data stream is 67 bits wide, and the subcarrier is
contained in Bit 0 to Bit 21. Each bit is two clock cycles long.
PHASE = FIELD 1
21
F
F
320
SC
320
320
SC
F
PHASE = FIELD 4 OR 8
SC
PHASE = FIELD 4 OR 8
PHASE = FIELD 1
TIMING RESET PULSE
F
SC
RESET PULSE
ADV7342/ADV7343