adv7342 Analog Devices, Inc., adv7342 Datasheet - Page 46

• Manufacturer Part Number: adv7342
• Description: Multiformat Video Encoder Six, 11-bit, 297 Mhz Dacs
• Manufacturer: Analog Devices, Inc.

ADV7342/ADV7343
Whether the ED/HD Y data is clocked in upon the rising
or falling edge of CLKIN_B is determined by Subaddress 0x01,
Bits[2:1] (See the input sequence shown in Figure 52 and
Figure 53).
Figure 56. Simultaneous SD and HD Example Application
Figure 55. Simultaneous SD and ED Example Application
DECODER
DECODER
DECODER
DECODER
HDTV
HDTV
SDTV
SDTV
1080i
1035i
1080i
1035i
720p
720p
OR
OR
OR
OR
74.25MHz
74.25MHz
CrCb
27MHz
YCrCb
CrCb
Y
27MHz
YCrCb
CrCb
Y
10
10
10
10
3
3
10
10
2
2
S_VSYNC,
S_HSYNC
CLKIN_A
S[7:0]
C[7:0]
Y[7:0]
P_HSYNC,
P_BLANK
CLKIN_B
S_HSYNC
CLKIN_A
S[7:0]
C[7:0]
Y[7:0]
P_HSYNC,
P_BLANK
CLKIN_B
P_VSYNC,
S_VSYNC,
P_VSYNC,
ADV7342/
ADV7342/
ADV7343
ADV7343
Rev. 0 | Page 46 of 88
ENHANCED DEFINITION ONLY (AT 54 MHz)
Subaddress 0x01, Bits[6:4] = 111
Enhanced definition (ED) YCrCb data can be input in an
interleaved 4:2:2 format on an 8-bit bus at a rate of 54 MHz.
A 54 MHz clock signal must be provided on the CLKIN_A pin.
Input synchronization signals are provided on the P_HSYNC ,
P_VSYNC , and P_BLANK pins.
The interleaved pixel data is input on Pin Y7 to Pin Y0, with Y0
being the LSB.
CLKIN_A
Y[7:0]
Figure 57. ED Only (at 54 MHz) Input Sequence (EAV/SAV)
Figure 58. ED Only (at 54 MHz) Example Application
INTERLACED TO
PROGRESSIVE
3FF
DECO DER
MPEG2
YCrCb
00
54MHz
YCrCb
00
10
XY
3
Cb0
P_HSYNC,
P_BLANK
P_VSYNC,
CLKIN_A
Y[7:0]
ADV7342/
ADV7343
Y0
Cr0
Y1