adv7188 Analog Devices, Inc., adv7188 Datasheet - Page 50

• Manufacturer Part Number: adv7188
• Description: Multiformat Sdtv Video Decoder With Fast Switch Overlay Support
• Manufacturer: Analog Devices, Inc.

ADV7188
For all NTSC/PAL vsync timing controls, both the V bit in the
AV code and the vsync on the VS pin are modified.
NFTOGDELO, NTSC Field Toggle Delay on Odd Field,
Address 0xE7 [7]
0 (default)—No delay.
1—Delays the field toggle/transition on an odd field by a line
relative to NFTOG.
NFTOGDELE, NTSC Field Toggle Delay on Even Field,
Address 0xE7 [6]
0—No delay.
1 (default)—Delays the field toggle/transition on an even field
by a line relative to NFTOG.
Table 63. Recommended User Settings for PAL (see Figure 33)
Register
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0xE8
0xE9
0xEA
NOT VALID FOR USER
PROGRAMMING
ADVANCE TOGGLE OF
FIELD BY NFTOG[4:0]
NFTOGDELO
ADDITIONAL
DELAY BY
1 LINE
YES
Figure 31. NTSC Field Toggle
1
1
0
NFTOGSIGN
ODD FIELD?
TOGGLE
FIELD
0
FIELD BY NFTOG[4:0]
DELAY TOGGLE OF
Register Name
Vsync Field Control 1
Vsync Field Control 2
Vsync Field Control 3
Hsync Position 1
Hsync Position 2
Hsync Position 3
Polarity
PAL V bit begin
PAL V bit end
PAL F bit toggle
NFTOGDELE
ADDITIONAL
DELAY BY
0
1 LINE
NO
1
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NFTOGSIGN, NTSC Field Toggle Sign, Address 0xE7 [5]
0—Delays the field transition. Set for manual programming.
1 (default)—Advances the field transition. Not recommended
for user programming.
NFTOG [4:0], NTSC Field Toggle, Address 0xE7 [4:0]
The default value of NFTOG is 00011, indicating the NTSC
field toggle position.
For all NTSC/PAL field timing controls, both the F bit in the
AV code and the field signal on the FIELD/DE pin are
modified.
PVBEGDELO, PAL Vsync Begin Delay on Odd Field,
Address 0xE8 [7]
0 (default)—No delay.
1—Delays vsync going high on an odd field by a line relative to
PVBEG.
PVBEGDELE, PAL Vsync Begin Delay on Even Field,
Address 0xE8 [6]
0 (default)—No delay.
1 (default)—Delays vsync going high on an even field by a line
relative to PVBEG.
PVBEGSIGN, PAL Vsync Begin Sign, Address 0xE8 [5]
0—Delays the beginning of vsync. Set for user manual
programming.
1 (default)—Advances the beginning of vsync. Not
recommended for user programming.
PVBEG [4:0], PAL Vsync Begin, Address 0xE8 [4:0]
The default value of PVBEG is 00101, indicating the PAL vsync
begin position.
For all NTSC/PAL vsync timing controls, both the V bit in the
AV code and the vsync on the VS pin are modified.
Write
0x1A
0x81
0x84
0x00
0x00
0x7D
0xA1
0x41
0x84
0x06