as8510 austriamicrosystems, as8510 Datasheet - Page 22

• Manufacturer Part Number: as8510
• Description: Data Acquisition Device For Battery Sensors
• Manufacturer: austriamicrosystems

AS8510
Datasheet - D e t a i l e d D e s c r i p t i o n
7.5 Reference-Voltage
Band gap-reference voltage is used for the ADC as a reference and for the generation of the current for external temperature measurement.
7.6 Oscillators
A High-speed oscillator (HS) generates the oversampling clock. For internal state machine and Interrupt generation, a low-speed Oscillator (LS)
is also available.
7.7 Power-On Reset
The AS8510 has PORs, APOR and DPOR on analog and digital power supplies respectively. On PORs of both supplies, initialization sequence
happens and the system status is shown in state diagram
As shown in the state diagram, the system is in RESET state until DPOR output goes to logic HIGH and subsequently until APOR output goes to
logic HIGH. Once analog power supply is available, the system goes into OTP_INT state and loads the default values into the control and data
registers and goes into STOP state. If analog POR, APOR goes low at any time, the system goes into RESET state. In the STOP state, the
AS8510 can be programmed and by giving start command it starts working following the state machine.
7.8 4-Wire Serial Port Interface
The SPI interface is used as interface between the AS8510 and an external micro-controller to configure the device and access the status
information. The micro-controller begins communication with the SPI which is configured as a slave. The SPI protocol is simple and the length of
each frame is an integer multiple of bytes except when a transmission is started. Each frame has 1 command bit, 7 address/configuration bits,
and one or more data bytes. The edge of CS and the level of SCLK during the start of a SPI transaction, determine the edge on which the data is
transferred from the SPI and the edge on which the data is sampled by the slave.
edges of SCLK.
falling edge of CS.
Table 29. CS and SCLK
Figure 9. Protocol for Serial Data Write with Length = 1
www.austriamicrosystems.com/AS8510
FALL
FALL
ANY
CS
Figure 9
SCLK
SDO
SDI
CS
shows the falling edge and rising edge for data transfer and data sampling respectively, when SCLK is HIGH on the
SCLK
HIGH
LOW
ANY
0
A6
Transfer edge
A5
A4
Serial data transferred on rising edge of SPI clock. Sampled at falling edge of SPI clock.
Serial data transferred on falling edge of SPI clock. Sampled at rising edge of SPI clock.
Serial data transfer edge is unchanged.
A3
(see Figure
Sampling edge
A2
A1
Revision 3.4
4).
A0
D7
Table 29
D6
D5
describes the setting of the transfer and sampling
Description
D4
D3
D2
D1
Data D7 – D0 is moved
to Address A4..A0 here
D0
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